[Mesa-dev] [PATCH] radv: trivial tidy ups

[Timothy Arceri]

---
 src/amd/vulkan/radv_pipeline.c       | 6 +-----
 src/amd/vulkan/radv_pipeline_cache.c | 1 +
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 723c32c..06e7446 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -34,20 +34,21 @@
 #include <llvm-c/Core.h>
 #include <llvm-c/TargetMachine.h>
 
 #include "sid.h"
 #include "r600d_common.h"
 #include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "ac_nir_to_llvm.h"
 #include "vk_format.h"
 #include "util/debug.h"
+
 void radv_shader_variant_destroy(struct radv_device *device,
                                  struct radv_shader_variant *variant);
 
 static const struct nir_shader_compiler_options nir_options = {
 	.vertex_id_zero_based = true,
 	.lower_scmp = true,
 	.lower_flrp32 = true,
 	.lower_fsat = true,
 	.lower_pack_snorm_2x16 = true,
 	.lower_pack_snorm_4x8 = true,
@@ -243,28 +244,24 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		/* Now that we've deleted all but the main function, we can go ahead and
 		 * lower the rest of the constant initializers.
 		 */
 		NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 		NIR_PASS_V(nir, nir_lower_system_values);
 	}
 
 	/* Vulkan uses the separate-shader linking model */
 	nir->info->separate_shader = true;
 
-	//   nir = brw_preprocess_nir(compiler, nir);
-
 	nir_shader_gather_info(nir, entry_point->impl);
 
 	nir_variable_mode indirect_mask = 0;
-	//   if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
 	indirect_mask |= nir_var_shader_in;
-	//   if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
 	indirect_mask |= nir_var_local;
 
 	nir_lower_indirect_derefs(nir, indirect_mask);
 
 	static const nir_lower_tex_options tex_options = {
 	  .lower_txp = ~0,
 	};
 
 	nir_lower_tex(nir, &tex_options);
 
@@ -1524,21 +1521,20 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 	const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
 	struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
 	for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
 		gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
 		pStages[stage] = &pCreateInfo->pStages[i];
 		modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
 	}
 
 	radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
 
-	/* */
 	if (modules[MESA_SHADER_VERTEX]) {
 		bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
 		union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
 
 		pipeline->shaders[MESA_SHADER_VERTEX] =
 			 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
 					       pStages[MESA_SHADER_VERTEX]->pName,
 					       MESA_SHADER_VERTEX,
 					       pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
 					       pipeline->layout, &key);
diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index 7fc4e78..296301d 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -298,20 +298,21 @@ radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 	return variant;
 }
 
 struct cache_header {
 	uint32_t header_size;
 	uint32_t header_version;
 	uint32_t vendor_id;
 	uint32_t device_id;
 	uint8_t  uuid[VK_UUID_SIZE];
 };
+
 void
 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 			 const void *data, size_t size)
 {
 	struct radv_device *device = cache->device;
 	struct cache_header header;
 
 	if (size < sizeof(header))
 		return;
 	memcpy(&header, data, sizeof(header));
-- 
2.9.3