[Mesa-dev] [PATCH 2/2] intel/debug: Add a common INTEL_DEBUG=nohiz option
Jason Ekstrand
jason at jlekstrand.net
Tue Mar 14 14:55:02 UTC 2017
The GL driver had a driconf option (which doesn't make much sense) and
the Vulkan driver had a hand-rolled environment variable. Instead,
let's tie both into the INTEL_DEBUG mechanism and unify things.
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
src/intel/vulkan/anv_image.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 4 ----
5 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index 1e0ba57..f90f00d 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -82,6 +82,7 @@ static const struct debug_control debug_control[] = {
{ "l3", DEBUG_L3 },
{ "do32", DEBUG_DO32 },
{ "norbc", DEBUG_NO_RBC },
+ { "nohiz", DEBUG_NO_HIZ },
{ NULL, 0 }
};
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index db13a06..d007aeb 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -78,6 +78,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_L3 (1ull << 36)
#define DEBUG_DO32 (1ull << 37)
#define DEBUG_NO_RBC (1ull << 38)
+#define DEBUG_NO_HIZ (1ull << 39)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 931ee22..7be988a 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -198,7 +198,7 @@ make_surface(const struct anv_device *dev,
anv_perf_warn("Implement multi-arrayLayer HiZ clears and resolves");
} else if (dev->info.gen == 8 && vk_info->samples > 1) {
anv_perf_warn("Enable gen8 multisampled HiZ");
- } else if (env_var_as_boolean("INTEL_VK_HIZ", true)) {
+ } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
assert(image->aux_surface.isl.size == 0);
ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
&image->aux_surface.isl);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 0e882ca..32cfb2e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -880,7 +880,7 @@ brw_process_driconf_options(struct brw_context *brw)
break;
}
- if (!driQueryOptionb(options, "hiz")) {
+ if (INTEL_DEBUG & DEBUG_NO_HIZ) {
brw->has_hiz = false;
/* On gen6, you can only do separate stencil with HIZ. */
if (brw->gen == 6)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 21786eb..10dab23 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -56,10 +56,6 @@ DRI_CONF_BEGIN
DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
DRI_CONF_DESC_END
DRI_CONF_OPT_END
-
- DRI_CONF_OPT_BEGIN_B(hiz, "true")
- DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
- DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
--
2.5.0.400.gff86faf
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