[Mesa-dev] [PATCH 2/3] anv: Flush caches prior to PIPELINE_SELECT on all gens

Jason Ekstrand jason at jlekstrand.net
Wed Mar 15 18:58:52 UTC 2017


The programming note that says we need to do this still exists in the
SkyLake PRM and, from looking at the bspec, seems to apply to all
hardware generations SNB+.  Also, this seems to be the cause of some of
the GPU hangs we've been seeing in GL with the "Car Chase" benchmark.

Reported-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: "17.0 13.0" <mesa-stable at lists.freedesktop.org>
---
 src/intel/vulkan/genX_cmd_buffer.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 2e95b98..a23fcba 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2040,8 +2040,8 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer,
     */
    if (pipeline == GPGPU)
       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
+#endif
 
-#elif GEN_GEN <= 7
    /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
     * PIPELINE_SELECT [DevBWR+]":
     *
@@ -2067,7 +2067,6 @@ flush_pipeline_before_pipeline_select(struct anv_cmd_buffer *cmd_buffer,
       pc.InstructionCacheInvalidateEnable = true;
       pc.PostSyncOperation                = NoWrite;
    }
-#endif
 }
 
 void
-- 
2.5.0.400.gff86faf



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