[Mesa-dev] [PATCH v2 5/5] i965: Drop AUB_TRACE_* stuff.
Kenneth Graunke
kenneth at whitecape.org
Mon Mar 20 22:04:20 UTC 2017
This was used for aubdumping (deleted a while ago) and INTEL_DEBUG=bat
decoding (deleted recently).
While we're changing parameters, delete the wrapper macro and make the
actual function brw_state_batch instead of __brw_state_batch.
This subsumes a patch by Emil Velikov to drop this from BLORP.
---
src/intel/blorp/blorp_genX_exec.h | 12 +++++-------
src/intel/vulkan/genX_blorp_exec.c | 1 -
src/mesa/drivers/dri/i965/brw_binding_tables.c | 7 +++----
src/mesa/drivers/dri/i965/brw_cc.c | 6 ++----
src/mesa/drivers/dri/i965/brw_clip_state.c | 6 ++----
src/mesa/drivers/dri/i965/brw_context.h | 4 +---
src/mesa/drivers/dri/i965/brw_gs_state.c | 3 +--
src/mesa/drivers/dri/i965/brw_sampler_state.c | 14 +++++---------
src/mesa/drivers/dri/i965/brw_sf_state.c | 6 ++----
src/mesa/drivers/dri/i965/brw_state.h | 11 ++---------
src/mesa/drivers/dri/i965/brw_state_batch.c | 11 ++++-------
src/mesa/drivers/dri/i965/brw_vs_state.c | 3 +--
src/mesa/drivers/dri/i965/brw_wm_state.c | 3 +--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 ++++++++----------
src/mesa/drivers/dri/i965/gen6_cc.c | 6 ++----
src/mesa/drivers/dri/i965/gen6_constant_state.c | 5 ++---
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 3 +--
src/mesa/drivers/dri/i965/gen6_gs_state.c | 3 +--
src/mesa/drivers/dri/i965/gen6_scissor_state.c | 3 +--
src/mesa/drivers/dri/i965/gen6_sol.c | 6 ++----
src/mesa/drivers/dri/i965/gen6_viewport_state.c | 6 ++----
src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +--
src/mesa/drivers/dri/i965/gen6_wm_state.c | 3 +--
src/mesa/drivers/dri/i965/gen7_cs_state.c | 15 ++++++---------
src/mesa/drivers/dri/i965/gen7_ds_state.c | 3 +--
src/mesa/drivers/dri/i965/gen7_hs_state.c | 3 +--
src/mesa/drivers/dri/i965/gen7_viewport_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 +--
src/mesa/drivers/dri/i965/gen8_blend_state.c | 4 ++--
src/mesa/drivers/dri/i965/gen8_surface_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen8_viewport_state.c | 2 +-
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10 ++++------
32 files changed, 70 insertions(+), 123 deletions(-)
Now with more bogus code deleted :)
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index dc1b7735ab3..379146245d9 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -27,7 +27,6 @@
#include "blorp_priv.h"
#include "common/gen_device_info.h"
#include "common/gen_sample_positions.h"
-#include "intel_aub.h"
/**
* This file provides the blorp pipeline setup and execution functionality.
@@ -53,7 +52,6 @@ blorp_emit_reloc(struct blorp_batch *batch,
static void *
blorp_alloc_dynamic_state(struct blorp_batch *batch,
- enum aub_state_struct_type type,
uint32_t size,
uint32_t alignment,
uint32_t *offset);
@@ -916,7 +914,7 @@ blorp_emit_blend_state(struct blorp_batch *batch,
}
uint32_t offset;
- void *state = blorp_alloc_dynamic_state(batch, AUB_TRACE_BLEND_STATE,
+ void *state = blorp_alloc_dynamic_state(batch,
GENX(BLEND_STATE_length) * 4,
64, &offset);
GENX(BLEND_STATE_pack)(NULL, state, &blend);
@@ -951,7 +949,7 @@ blorp_emit_color_calc_state(struct blorp_batch *batch,
#endif
uint32_t offset;
- void *state = blorp_alloc_dynamic_state(batch, AUB_TRACE_CC_STATE,
+ void *state = blorp_alloc_dynamic_state(batch,
GENX(COLOR_CALC_STATE_length) * 4,
64, &offset);
GENX(COLOR_CALC_STATE_pack)(NULL, state, &cc);
@@ -1031,7 +1029,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &ds);
#else
uint32_t offset;
- void *state = blorp_alloc_dynamic_state(batch, AUB_TRACE_DEPTH_STENCIL_STATE,
+ void *state = blorp_alloc_dynamic_state(batch,
GENX(DEPTH_STENCIL_STATE_length) * 4,
64, &offset);
GENX(DEPTH_STENCIL_STATE_pack)(NULL, state, &ds);
@@ -1201,7 +1199,7 @@ blorp_emit_sampler_state(struct blorp_batch *batch,
};
uint32_t offset;
- void *state = blorp_alloc_dynamic_state(batch, AUB_TRACE_SAMPLER_STATE,
+ void *state = blorp_alloc_dynamic_state(batch,
GENX(SAMPLER_STATE_length) * 4,
32, &offset);
GENX(SAMPLER_STATE_pack)(NULL, state, &sampler);
@@ -1349,7 +1347,7 @@ blorp_emit_viewport_state(struct blorp_batch *batch,
{
uint32_t cc_vp_offset;
- void *state = blorp_alloc_dynamic_state(batch, AUB_TRACE_CC_VP_STATE,
+ void *state = blorp_alloc_dynamic_state(batch,
GENX(CC_VIEWPORT_length) * 4, 32,
&cc_vp_offset);
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index 6b46a1e10ad..1d07fd7b5ea 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -66,7 +66,6 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
static void *
blorp_alloc_dynamic_state(struct blorp_batch *batch,
- enum aub_state_struct_type type,
uint32_t size,
uint32_t alignment,
uint32_t *offset)
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 4c4c9c22ca6..c0a763d0aeb 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -71,10 +71,9 @@ brw_upload_binding_table(struct brw_context *brw,
brw->shader_time.bo, 0, ISL_FORMAT_RAW,
brw->shader_time.bo->size, 1, true);
}
- uint32_t *bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- prog_data->binding_table.size_bytes,
- 32,
- &stage_state->bind_bo_offset);
+ uint32_t *bind =
+ brw_state_batch(brw, prog_data->binding_table.size_bytes,
+ 32, &stage_state->bind_bo_offset);
/* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
memcpy(bind, stage_state->surf_offset,
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index c3b00e1b605..ae927011896 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -47,8 +47,7 @@ brw_upload_cc_vp(struct brw_context *brw)
/* BRW_NEW_VIEWPORT_COUNT */
const unsigned viewport_count = brw->clip.viewport_count;
- ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
- sizeof(*ccv) * viewport_count, 32,
+ ccv = brw_state_batch(brw, sizeof(*ccv) * viewport_count, 32,
&brw->cc.vp_offset);
/* _NEW_TRANSFORM */
@@ -116,8 +115,7 @@ static void upload_cc_unit(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
struct brw_cc_unit_state *cc;
- cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
- sizeof(*cc), 64, &brw->cc.state_offset);
+ cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
/* _NEW_STENCIL | _NEW_BUFFERS */
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 39c149c9762..3747b6040c4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -40,8 +40,7 @@ upload_clip_vp(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
struct brw_clipper_viewport *vp;
- vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
- sizeof(*vp), 32, &brw->clip.vp_offset);
+ vp = brw_state_batch(brw, sizeof(*vp), 32, &brw->clip.vp_offset);
const float maximum_post_clamp_delta = 4096;
float gbx = maximum_post_clamp_delta / ctx->ViewportArray[0].Width;
@@ -66,8 +65,7 @@ brw_upload_clip_unit(struct brw_context *brw)
upload_clip_vp(brw);
- clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
- sizeof(*clip), 32, &brw->clip.state_offset);
+ clip = brw_state_batch(brw, sizeof(*clip), 32, &brw->clip.state_offset);
memset(clip, 0, sizeof(*clip));
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_CLIP_PROG_DATA */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a119d79a7e5..a042e4b2ff6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -38,7 +38,6 @@
#include "main/mtypes.h"
#include "brw_structs.h"
#include "compiler/brw_compiler.h"
-#include "intel_aub.h"
#include "isl/isl.h"
#include "blorp/blorp.h"
@@ -1699,8 +1698,7 @@ void
gen6_upload_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_stage_prog_data *prog_data,
- struct brw_stage_state *stage_state,
- enum aub_state_struct_type type);
+ struct brw_stage_state *stage_state);
bool
gen9_use_linear_1d_layout(const struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 8e3bf1ef651..acd0f5f877d 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -40,8 +40,7 @@ brw_upload_gs_unit(struct brw_context *brw)
{
struct brw_gs_unit_state *gs;
- gs = brw_state_batch(brw, AUB_TRACE_GS_STATE,
- sizeof(*gs), 32, &brw->ff_gs.state_offset);
+ gs = brw_state_batch(brw, sizeof(*gs), 32, &brw->ff_gs.state_offset);
memset(gs, 0, sizeof(*gs));
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index b99a89893f6..6296512b22b 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -290,8 +290,7 @@ upload_default_color(struct brw_context *brw,
* format. This matches the sampler->BorderColor union exactly; just
* memcpy the values.
*/
- uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
- 4 * 4, 64, sdc_offset);
+ uint32_t *sdc = brw_state_batch(brw, 4 * 4, 64, sdc_offset);
memcpy(sdc, color.ui, 4 * 4);
} else if (brw->is_haswell && (is_integer_format || is_stencil_sampling)) {
/* Haswell's integer border color support is completely insane:
@@ -302,8 +301,7 @@ upload_default_color(struct brw_context *brw,
* has the "Integer Surface Format" bit set. Even then, the
* arrangement of the RGBA data devolves into madness.
*/
- uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
- 20 * 4, 512, sdc_offset);
+ uint32_t *sdc = brw_state_batch(brw, 20 * 4, 512, sdc_offset);
memset(sdc, 0, 20 * 4);
sdc = &sdc[16];
@@ -359,8 +357,7 @@ upload_default_color(struct brw_context *brw,
} else if (brw->gen == 5 || brw->gen == 6) {
struct gen5_sampler_default_color *sdc;
- sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
- sizeof(*sdc), 32, sdc_offset);
+ sdc = brw_state_batch(brw, sizeof(*sdc), 32, sdc_offset);
memset(sdc, 0, sizeof(*sdc));
@@ -394,8 +391,7 @@ upload_default_color(struct brw_context *brw,
sdc->f[2] = color.f[2];
sdc->f[3] = color.f[3];
} else {
- float *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
- 4 * 4, 32, sdc_offset);
+ float *sdc = brw_state_batch(brw, 4 * 4, 32, sdc_offset);
memcpy(sdc, color.f, 4 * 4);
}
}
@@ -596,7 +592,7 @@ brw_upload_sampler_state_table(struct brw_context *brw,
const int dwords = 4;
const int size_in_bytes = dwords * sizeof(uint32_t);
- uint32_t *sampler_state = brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
+ uint32_t *sampler_state = brw_state_batch(brw,
sampler_count * size_in_bytes,
32, &stage_state->sampler_offset);
memset(sampler_state, 0, sampler_count * size_in_bytes);
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 89406fc9cb8..5580baa0ea1 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -48,8 +48,7 @@ static void upload_sf_vp(struct brw_context *brw)
float scale[3], translate[3];
const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
- sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
- sizeof(*sfv), 32, &brw->sf.vp_offset);
+ sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
memset(sfv, 0, sizeof(*sfv));
/* Accessing the fields Width and Height of gl_framebuffer to produce the
@@ -138,8 +137,7 @@ static void upload_sf_unit( struct brw_context *brw )
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
- sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
- sizeof(*sf), 64, &brw->sf.state_offset);
+ sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
memset(sf, 0, sizeof(*sf));
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 1eb2a0d0cb6..99e50f3a433 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -252,15 +252,8 @@ void brw_print_program_cache(struct brw_context *brw);
#define BRW_BATCH_STRUCT(brw, s) \
intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
-void *__brw_state_batch(struct brw_context *brw,
- enum aub_state_struct_type type,
- int size,
- int alignment,
- int index,
- uint32_t *out_offset);
-#define brw_state_batch(brw, type, size, alignment, out_offset) \
- __brw_state_batch(brw, type, size, alignment, 0, out_offset)
-
+void *brw_state_batch(struct brw_context *brw,
+ int size, int alignment, uint32_t *out_offset);
uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset);
/* brw_wm_surface_state.c */
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 0408a2ae437..5b6f3af93d8 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -59,13 +59,10 @@ brw_state_batch_size(struct brw_context *brw, uint32_t offset)
* buffers in at the top of the batchbuffer.
*/
void *
-__brw_state_batch(struct brw_context *brw,
- enum aub_state_struct_type type,
- int size,
- int alignment,
- int index,
- uint32_t *out_offset)
-
+brw_state_batch(struct brw_context *brw,
+ int size,
+ int alignment,
+ uint32_t *out_offset)
{
struct intel_batchbuffer *batch = &brw->batch;
uint32_t offset;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index d0d2695a496..ff0a81ff877 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -47,8 +47,7 @@ brw_upload_vs_unit(struct brw_context *brw)
struct brw_vs_unit_state *vs;
- vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
- sizeof(*vs), 32, &stage_state->state_offset);
+ vs = brw_state_batch(brw, sizeof(*vs), 32, &stage_state->state_offset);
memset(vs, 0, sizeof(*vs));
/* BRW_NEW_PROGRAM_CACHE | BRW_NEW_VS_PROG_DATA */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 6f2ccabaa00..5ec72360cc7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -85,8 +85,7 @@ brw_upload_wm_unit(struct brw_context *brw)
brw_wm_prog_data(brw->wm.base.prog_data);
struct brw_wm_unit_state *wm;
- wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
- sizeof(*wm), 32, &brw->wm.base.state_offset);
+ wm = brw_state_batch(brw, sizeof(*wm), 32, &brw->wm.base.state_offset);
memset(wm, 0, sizeof(*wm));
if (prog_data->dispatch_8 && prog_data->dispatch_16) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 16d32960c71..1d4953e64ad 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -156,10 +156,10 @@ brw_emit_surface_state(struct brw_context *brw,
clear_color = intel_miptree_get_isl_clear_color(brw, mt);
}
- void *state = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- brw->isl_dev.ss.size,
- brw->isl_dev.ss.align,
- surf_index, surf_offset);
+ void *state = brw_state_batch(brw,
+ brw->isl_dev.ss.size,
+ brw->isl_dev.ss.align,
+ surf_offset);
isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
.address = mt->bo->offset64 + offset,
@@ -654,7 +654,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
unsigned pitch,
bool rw)
{
- uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ uint32_t *dw = brw_state_batch(brw,
brw->isl_dev.ss.size,
brw->isl_dev.ss.align,
out_offset);
@@ -781,8 +781,7 @@ brw_update_sol_surface(struct brw_context *brw,
drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
offset_bytes,
buffer_obj->Size - offset_bytes);
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- out_offset);
+ uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
uint32_t pitch_minus_1 = 4*stride_dwords - 1;
size_t size_dwords = buffer_obj->Size / 4;
uint32_t buffer_size_minus_1, width, height, depth, surface_format;
@@ -918,8 +917,7 @@ brw_emit_null_surface_state(struct brw_context *brw,
drm_intel_bo *bo = NULL;
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- out_offset);
+ uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
if (samples > 1) {
/* On Gen6, null render targets seem to cause GPU hangs when
@@ -1017,7 +1015,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
}
}
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
+ surf = brw_state_batch(brw, 6 * 4, 32, &offset);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 0c38930ec2b..0e0d05e8146 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -55,8 +55,7 @@ gen6_upload_blend_state(struct brw_context *brw)
nr_draw_buffers = 1;
size = sizeof(*blend) * nr_draw_buffers;
- blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
- size, 64, &brw->cc.blend_state_offset);
+ blend = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
memset(blend, 0, size);
@@ -258,8 +257,7 @@ gen6_upload_color_calc_state(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
struct gen6_color_calc_state *cc;
- cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
- sizeof(*cc), 64, &brw->cc.state_offset);
+ cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
/* _NEW_COLOR */
diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 6c0c32b26f7..40941c17711 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -119,8 +119,7 @@ void
gen6_upload_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_stage_prog_data *prog_data,
- struct brw_stage_state *stage_state,
- enum aub_state_struct_type type)
+ struct brw_stage_state *stage_state)
{
struct gl_context *ctx = &brw->ctx;
@@ -137,7 +136,7 @@ gen6_upload_push_constants(struct brw_context *brw,
gl_constant_value *param;
int i;
- param = brw_state_batch(brw, type,
+ param = brw_state_batch(brw,
prog_data->nr_params * sizeof(gl_constant_value),
32, &stage_state->push_const_offset);
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 79d4d5da162..0f9626cd15a 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -41,8 +41,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
/* _NEW_BUFFERS */
depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
- ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
- sizeof(*ds), 64,
+ ds = brw_state_batch(brw, sizeof(*ds), 64,
&brw->cc.depth_stencil_state_offset);
memset(ds, 0, sizeof(*ds));
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index e9179152b32..0cdfcf56010 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -44,8 +44,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY);
- gen6_upload_push_constants(brw, &gp->program, prog_data, stage_state,
- AUB_TRACE_VS_CONSTANTS);
+ gen6_upload_push_constants(brw, &gp->program, prog_data, stage_state);
}
if (brw->gen >= 7)
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 860445a2b43..3407f6a93f7 100644
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -45,8 +45,7 @@ gen6_upload_scissor_state(struct brw_context *brw)
/* BRW_NEW_VIEWPORT_COUNT */
const unsigned viewport_count = brw->clip.viewport_count;
- scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
- sizeof(*scissor) * viewport_count, 32,
+ scissor = brw_state_batch(brw, sizeof(*scissor) * viewport_count, 32,
&scissor_state_offset);
/* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index 132f0696e35..d117e1c0eca 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -131,8 +131,7 @@ brw_gs_upload_binding_table(struct brw_context *brw)
* space for the binding table. Anyway, in this case we know that we only
* use BRW_MAX_SOL_BINDINGS surfaces at most.
*/
- bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- sizeof(uint32_t) * BRW_MAX_SOL_BINDINGS,
+ bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_MAX_SOL_BINDINGS,
32, &brw->ff_gs.bind_bo_offset);
/* BRW_NEW_SURFACES */
@@ -160,8 +159,7 @@ brw_gs_upload_binding_table(struct brw_context *brw)
/* Might want to calculate nr_surfaces first, to avoid taking up so much
* space for the binding table.
*/
- bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- sizeof(uint32_t) * BRW_MAX_SURFACES,
+ bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_MAX_SURFACES,
32, &brw->gs.base.bind_bo_offset);
/* BRW_NEW_SURFACES */
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 569e5bd4a15..41cc459f19a 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -132,13 +132,11 @@ gen6_upload_sf_and_clip_viewports(struct brw_context *brw)
const uint32_t fb_width = _mesa_geometric_width(ctx->DrawBuffer);
const uint32_t fb_height = _mesa_geometric_height(ctx->DrawBuffer);
- sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
- sizeof(*sfv) * viewport_count,
+ sfv = brw_state_batch(brw, sizeof(*sfv) * viewport_count,
32, &brw->sf.vp_offset);
memset(sfv, 0, sizeof(*sfv) * viewport_count);
- clv = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
- sizeof(*clv) * viewport_count,
+ clv = brw_state_batch(brw, sizeof(*clv) * viewport_count,
32, &brw->clip.vp_offset);
if (render_to_fbo) {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 837762d3910..17b8118d45f 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -45,8 +45,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_VERTEX);
- gen6_upload_push_constants(brw, &vp->program, prog_data, stage_state,
- AUB_TRACE_VS_CONSTANTS);
+ gen6_upload_push_constants(brw, &vp->program, prog_data, stage_state);
if (brw->gen >= 7) {
if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index cda7c11d934..aabae70d10b 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -49,8 +49,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT);
- gen6_upload_push_constants(brw, &fp->program, prog_data,
- stage_state, AUB_TRACE_WM_CONSTANTS);
+ gen6_upload_push_constants(brw, &fp->program, prog_data, stage_state);
if (brw->gen >= 7) {
gen7_upload_constant_state(brw, &brw->wm.base, true,
diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index d8df6bb8d29..48b3d8715a6 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -40,8 +40,7 @@ brw_upload_cs_state(struct brw_context *brw)
return;
uint32_t offset;
- uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 64, &offset);
+ uint32_t *desc = (uint32_t*) brw_state_batch(brw, 8 * 4, 64, &offset);
struct brw_stage_state *stage_state = &brw->cs.base;
struct brw_stage_prog_data *prog_data = stage_state->prog_data;
struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
@@ -55,9 +54,8 @@ brw_upload_cs_state(struct brw_context *brw)
brw->shader_time.bo->size, 1, true);
}
- uint32_t *bind = (uint32_t*) brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- prog_data->binding_table.size_bytes,
- 32, &stage_state->bind_bo_offset);
+ uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
+ 32, &stage_state->bind_bo_offset);
uint32_t dwords = brw->gen < 8 ? 8 : 9;
BEGIN_BATCH(dwords);
@@ -211,8 +209,7 @@ static void
brw_upload_cs_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_cs_prog_data *cs_prog_data,
- struct brw_stage_state *stage_state,
- enum aub_state_struct_type type)
+ struct brw_stage_state *stage_state)
{
struct gl_context *ctx = &brw->ctx;
const struct brw_stage_prog_data *prog_data =
@@ -231,7 +228,7 @@ brw_upload_cs_push_constants(struct brw_context *brw,
gl_constant_value *param = (gl_constant_value*)
- brw_state_batch(brw, type, ALIGN(cs_prog_data->push.total.size, 64),
+ brw_state_batch(brw, ALIGN(cs_prog_data->push.total.size, 64),
64, &stage_state->push_const_offset);
assert(param);
@@ -288,7 +285,7 @@ gen7_upload_cs_push_constants(struct brw_context *brw)
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
brw_upload_cs_push_constants(brw, &cp->program, cs_prog_data,
- stage_state, AUB_TRACE_WM_CONSTANTS);
+ stage_state);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c
index 9d7f5315de4..04d7a868fbe 100644
--- a/src/mesa/drivers/dri/i965/gen7_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_ds_state.c
@@ -38,8 +38,7 @@ gen7_upload_tes_push_constants(struct brw_context *brw)
/* BRW_NEW_TES_PROG_DATA */
const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_EVAL);
- gen6_upload_push_constants(brw, &tep->program, prog_data, stage_state,
- AUB_TRACE_VS_CONSTANTS);
+ gen6_upload_push_constants(brw, &tep->program, prog_data, stage_state);
}
gen7_upload_constant_state(brw, stage_state, tep, _3DSTATE_CONSTANT_DS);
diff --git a/src/mesa/drivers/dri/i965/gen7_hs_state.c b/src/mesa/drivers/dri/i965/gen7_hs_state.c
index fadea2351da..765253f5620 100644
--- a/src/mesa/drivers/dri/i965/gen7_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_hs_state.c
@@ -40,8 +40,7 @@ gen7_upload_tcs_push_constants(struct brw_context *brw)
const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
_mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
- gen6_upload_push_constants(brw, &tcp->program, prog_data, stage_state,
- AUB_TRACE_VS_CONSTANTS);
+ gen6_upload_push_constants(brw, &tcp->program, prog_data, stage_state);
}
gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS);
diff --git a/src/mesa/drivers/dri/i965/gen7_viewport_state.c b/src/mesa/drivers/dri/i965/gen7_viewport_state.c
index 000f238f3fe..a3cb4541242 100644
--- a/src/mesa/drivers/dri/i965/gen7_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_viewport_state.c
@@ -46,7 +46,7 @@ gen7_upload_sf_clip_viewport(struct brw_context *brw)
const uint32_t fb_width = _mesa_geometric_width(ctx->DrawBuffer);
const uint32_t fb_height = _mesa_geometric_height(ctx->DrawBuffer);
- vp = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ vp = brw_state_batch(brw,
sizeof(*vp) * viewport_count, 64,
&brw->sf.vp_offset);
/* Also assign to clip.vp_offset in case something uses it. */
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index e30dbb336d9..c9d777bcc57 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -155,8 +155,7 @@ gen7_emit_null_surface_state(struct brw_context *brw,
* depth buffer’s corresponding state for all render target surfaces,
* including null.
*/
- uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
- out_offset);
+ uint32_t *surf = brw_state_batch(brw, 8 * 4, 32, out_offset);
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index 2e4e8bfed16..1fa8ba23fb3 100644
--- a/src/mesa/drivers/dri/i965/gen8_blend_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_blend_state.c
@@ -50,8 +50,8 @@ gen8_upload_blend_state(struct brw_context *brw)
nr_draw_buffers = 1;
int size = 4 + 8 * nr_draw_buffers;
- uint32_t *blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
- size, 64, &brw->cc.blend_state_offset);
+ uint32_t *blend =
+ brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
memset(blend, 0, size);
/* OpenGL specification 3.3 (page 196), section 4.1.3 says:
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index f8682932172..c2ac7c74a61 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -43,11 +43,9 @@
#include "isl/isl.h"
static uint32_t *
-gen8_allocate_surface_state(struct brw_context *brw,
- uint32_t *out_offset, int index)
+gen8_allocate_surface_state(struct brw_context *brw, uint32_t *out_offset)
{
- uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 64, 64, index, out_offset);
+ uint32_t *surf = brw_state_batch(brw, 64, 64, out_offset);
memset(surf, 0, 64);
return surf;
}
@@ -67,7 +65,7 @@ gen8_emit_null_surface_state(struct brw_context *brw,
unsigned samples,
uint32_t *out_offset)
{
- uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
+ uint32_t *surf = gen8_allocate_surface_state(brw, out_offset);
surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
ISL_FORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
diff --git a/src/mesa/drivers/dri/i965/gen8_viewport_state.c b/src/mesa/drivers/dri/i965/gen8_viewport_state.c
index 101ad2b110e..ffb14263337 100644
--- a/src/mesa/drivers/dri/i965/gen8_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_viewport_state.c
@@ -45,7 +45,7 @@ gen8_upload_sf_clip_viewport(struct brw_context *brw)
const uint32_t fb_width = _mesa_geometric_width(ctx->DrawBuffer);
const uint32_t fb_height = _mesa_geometric_height(ctx->DrawBuffer);
- float *vp = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ float *vp = brw_state_batch(brw,
16 * 4 * viewport_count,
64, &brw->sf.vp_offset);
/* Also assign to clip.vp_offset in case something uses it. */
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 0224d6e43df..35310fa03df 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -91,7 +91,6 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
static void *
blorp_alloc_dynamic_state(struct blorp_batch *batch,
- enum aub_state_struct_type type,
uint32_t size,
uint32_t alignment,
uint32_t *offset)
@@ -99,7 +98,7 @@ blorp_alloc_dynamic_state(struct blorp_batch *batch,
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
- return brw_state_batch(brw, type, size, alignment, offset);
+ return brw_state_batch(brw, size, alignment, offset);
}
static void
@@ -111,12 +110,12 @@ blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
- uint32_t *bt_map = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
+ uint32_t *bt_map = brw_state_batch(brw,
num_entries * sizeof(uint32_t), 32,
bt_offset);
for (unsigned i = 0; i < num_entries; i++) {
- surface_maps[i] = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ surface_maps[i] = brw_state_batch(brw,
state_size, state_alignment,
&(surface_offsets)[i]);
bt_map[i] = surface_offsets[i];
@@ -131,8 +130,7 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
struct brw_context *brw = batch->driver_batch;
uint32_t offset;
- void *data = brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
- size, 32, &offset);
+ void *data = brw_state_batch(brw, size, 32, &offset);
*addr = (struct blorp_address) {
.buffer = brw->batch.bo,
--
2.12.0
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