[Mesa-dev] [PATCH 001/140] amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spelling
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:42:11 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
---
src/amd/addrlib/r800/ciaddrlib.cpp | 110 ++++++++++++------------
src/amd/addrlib/r800/ciaddrlib.h | 12 +--
src/amd/addrlib/r800/siaddrlib.cpp | 168 ++++++++++++++++++-------------------
src/amd/addrlib/r800/siaddrlib.h | 8 +-
4 files changed, 149 insertions(+), 149 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index c726c4d..ae91e44 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file ciaddrlib.cpp
-* @brief Contains the implementation for the CIAddrLib class.
+* @brief Contains the implementation for the CiAddrLib class.
***************************************************************************************************
*/
#include "ciaddrlib.h"
#include "si_gb_reg.h"
#include "si_ci_vi_merged_enum.h"
#if BRAHMA_BUILD
@@ -149,72 +149,72 @@ static UINT_64 AddrInsertBits(
}
return ret;
}
/**
***************************************************************************************************
* AddrCIHwlInit
*
* @brief
-* Creates an CIAddrLib object.
+* Creates an CiAddrLib object.
*
* @return
-* Returns an CIAddrLib object pointer.
+* Returns an CiAddrLib object pointer.
***************************************************************************************************
*/
AddrLib* AddrCIHwlInit(const AddrClient* pClient)
{
- return CIAddrLib::CreateObj(pClient);
+ return CiAddrLib::CreateObj(pClient);
}
/**
***************************************************************************************************
-* CIAddrLib::CIAddrLib
+* CiAddrLib::CiAddrLib
*
* @brief
* Constructor
*
***************************************************************************************************
*/
-CIAddrLib::CIAddrLib(const AddrClient* pClient) :
- SIAddrLib(pClient),
+CiAddrLib::CiAddrLib(const AddrClient* pClient) :
+ SiAddrLib(pClient),
m_noOfMacroEntries(0),
m_allowNonDispThickModes(FALSE)
{
m_class = CI_ADDRLIB;
memset(&m_settings, 0, sizeof(m_settings));
}
/**
***************************************************************************************************
-* CIAddrLib::~CIAddrLib
+* CiAddrLib::~CiAddrLib
*
* @brief
* Destructor
***************************************************************************************************
*/
-CIAddrLib::~CIAddrLib()
+CiAddrLib::~CiAddrLib()
{
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeDccInfo
+* CiAddrLib::HwlComputeDccInfo
*
* @brief
* Compute DCC key size, base alignment
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE CIAddrLib::HwlComputeDccInfo(
+ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (m_settings.isVolcanicIslands && IsMacroTiled(pIn->tileMode))
{
UINT_64 dccFastClearSize = pIn->colorSurfSize >> 8;
ADDR_ASSERT(0 == (pIn->colorSurfSize & 0xff));
@@ -269,30 +269,30 @@ ADDR_E_RETURNCODE CIAddrLib::HwlComputeDccInfo(
else
{
returnCode = ADDR_NOTSUPPORTED;
}
return returnCode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeCmaskAddrFromCoord
+* CiAddrLib::HwlComputeCmaskAddrFromCoord
*
* @brief
* Compute tc compatible Cmask address from fmask ram address
*
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE CIAddrLib::HwlComputeCmaskAddrFromCoord(
+ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ///< [in] fmask addr/bpp/tile input
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut ///< [out] cmask address
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED;
if ((m_settings.isVolcanicIslands == TRUE) &&
(pIn->flags.tcCompatible == TRUE))
{
UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo);
@@ -312,29 +312,29 @@ ADDR_E_RETURNCODE CIAddrLib::HwlComputeCmaskAddrFromCoord(
1);
pOut->addr = (metaNibbleAddress >> 1);
pOut->bitPosition = (metaNibbleAddress % 2) ? 4 : 0;
returnCode = ADDR_OK;
}
return returnCode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlConvertChipFamily
+* CiAddrLib::HwlConvertChipFamily
*
* @brief
* Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision
* @return
* AddrChipFamily
***************************************************************************************************
*/
-AddrChipFamily CIAddrLib::HwlConvertChipFamily(
+AddrChipFamily CiAddrLib::HwlConvertChipFamily(
UINT_32 uChipFamily, ///< [in] chip family defined in atiih.h
UINT_32 uChipRevision) ///< [in] chip revision defined in "asic_family"_id.h
{
AddrChipFamily family = ADDR_CHIP_FAMILY_CI;
switch (uChipFamily)
{
case FAMILY_CI:
m_settings.isSeaIsland = 1;
m_settings.isBonaire = ASICREV_IS_BONAIRE_M(uChipRevision);
@@ -362,31 +362,31 @@ AddrChipFamily CIAddrLib::HwlConvertChipFamily(
default:
ADDR_ASSERT(!"This should be a unexpected Fusion");
break;
}
return family;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlInitGlobalParams
+* CiAddrLib::HwlInitGlobalParams
*
* @brief
* Initializes global parameters
*
* @return
* TRUE if all settings are valid
*
***************************************************************************************************
*/
-BOOL_32 CIAddrLib::HwlInitGlobalParams(
+BOOL_32 CiAddrLib::HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
{
BOOL_32 valid = TRUE;
const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
valid = DecodeGbRegs(pRegValue);
// The following assignments for m_pipes is only for fail-safe, InitTileSettingTable should
// read the correct pipes from tile mode table
@@ -430,30 +430,30 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
if (valid)
{
valid = InitMacroTileCfgTable(pRegValue->pMacroTileConfig, pRegValue->noOfMacroEntries);
}
return valid;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlPostCheckTileIndex
+* CiAddrLib::HwlPostCheckTileIndex
*
* @brief
* Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
* tile mode/type/info and change the index if needed
* @return
* Tile index.
***************************************************************************************************
*/
-INT_32 CIAddrLib::HwlPostCheckTileIndex(
+INT_32 CiAddrLib::HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, ///< [in] Tile Info
AddrTileMode mode, ///< [in] Tile mode
AddrTileType type, ///< [in] Tile type
INT curIndex ///< [in] Current index assigned in HwlSetupTileInfo
) const
{
INT_32 index = curIndex;
if (mode == ADDR_TM_LINEAR_GENERAL)
{
@@ -520,29 +520,29 @@ INT_32 CIAddrLib::HwlPostCheckTileIndex(
if (index >= static_cast<INT_32>(m_noOfEntries))
{
index = TileIndexInvalid;
}
return index;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlSetupTileCfg
+* CiAddrLib::HwlSetupTileCfg
*
* @brief
* Map tile index to tile setting.
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE CIAddrLib::HwlSetupTileCfg(
+ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg(
INT_32 index, ///< [in] Tile index
INT_32 macroModeIndex, ///< [in] Index in macro tile mode table(CI)
ADDR_TILEINFO* pInfo, ///< [out] Tile Info
AddrTileMode* pMode, ///< [out] Tile mode
AddrTileType* pType ///< [out] Tile type
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
// Global flag to control usage of tileIndex
@@ -595,59 +595,59 @@ ADDR_E_RETURNCODE CIAddrLib::HwlSetupTileCfg(
*pType = pCfgTable->type;
}
}
}
return returnCode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeSurfaceInfo
+* CiAddrLib::HwlComputeSurfaceInfo
*
* @brief
* Entry of ci's ComputeSurfaceInfo
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE CIAddrLib::HwlComputeSurfaceInfo(
+ADDR_E_RETURNCODE CiAddrLib::HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
) const
{
// If tileIndex is invalid, force macroModeIndex to be invalid, too
if (pIn->tileIndex == TileIndexInvalid)
{
pOut->macroModeIndex = TileIndexInvalid;
}
- ADDR_E_RETURNCODE retCode = SIAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
+ ADDR_E_RETURNCODE retCode = SiAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
if (pOut->macroModeIndex == TileIndexNoMacroIndex)
{
pOut->macroModeIndex = TileIndexInvalid;
}
return retCode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlFmaskSurfaceInfo
+* CiAddrLib::HwlFmaskSurfaceInfo
* @brief
* Entry of r800's ComputeFmaskInfo
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE CIAddrLib::HwlComputeFmaskInfo(
+ADDR_E_RETURNCODE CiAddrLib::HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, ///< [in] input structure
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut ///< [out] output structure
)
{
ADDR_E_RETURNCODE retCode = ADDR_OK;
ADDR_TILEINFO tileInfo = {0};
ADDR_COMPUTE_FMASK_INFO_INPUT fmaskIn;
fmaskIn = *pIn;
@@ -713,91 +713,91 @@ ADDR_E_RETURNCODE CIAddrLib::HwlComputeFmaskInfo(
if (pOut->pTileInfo == &tileInfo)
{
pOut->pTileInfo = NULL;
}
return retCode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlFmaskPreThunkSurfInfo
+* CiAddrLib::HwlFmaskPreThunkSurfInfo
*
* @brief
* Some preparation before thunking a ComputeSurfaceInfo call for Fmask
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-VOID CIAddrLib::HwlFmaskPreThunkSurfInfo(
+VOID CiAddrLib::HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn, ///< [in] Input of fmask info
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut, ///< [in] Output of fmask info
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn, ///< [out] Input of thunked surface info
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut ///< [out] Output of thunked surface info
) const
{
pSurfIn->tileIndex = pFmaskIn->tileIndex;
pSurfOut->macroModeIndex = pFmaskOut->macroModeIndex;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlFmaskPostThunkSurfInfo
+* CiAddrLib::HwlFmaskPostThunkSurfInfo
*
* @brief
* Copy hwl extra field after calling thunked ComputeSurfaceInfo
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-VOID CIAddrLib::HwlFmaskPostThunkSurfInfo(
+VOID CiAddrLib::HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut, ///< [in] Output of surface info
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut ///< [out] Output of fmask info
) const
{
pFmaskOut->tileIndex = pSurfOut->tileIndex;
pFmaskOut->macroModeIndex = pSurfOut->macroModeIndex;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlDegradeThickTileMode
+* CiAddrLib::HwlDegradeThickTileMode
*
* @brief
* Degrades valid tile mode for thick modes if needed
*
* @return
* Suitable tile mode
***************************************************************************************************
*/
-AddrTileMode CIAddrLib::HwlDegradeThickTileMode(
+AddrTileMode CiAddrLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
) const
{
return baseTileMode;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlOverrideTileMode
+* CiAddrLib::HwlOverrideTileMode
*
* @brief
* Override THICK to THIN, for specific formats on CI
*
* @return
* Suitable tile mode
*
***************************************************************************************************
*/
-BOOL_32 CIAddrLib::HwlOverrideTileMode(
+BOOL_32 CiAddrLib::HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
AddrTileMode* pTileMode, ///< [in/out] pointer to the tile mode
AddrTileType* pTileType ///< [in/out] pointer to the tile type
) const
{
BOOL_32 bOverrided = FALSE;
AddrTileMode tileMode = *pTileMode;
// currently, all CI/VI family do not
// support ADDR_TM_PRT_2D_TILED_THICK,ADDR_TM_PRT_3D_TILED_THICK and
@@ -902,21 +902,21 @@ BOOL_32 CIAddrLib::HwlOverrideTileMode(
}
/**
***************************************************************************************************
* CiAddrLib::GetPrtSwitchP4Threshold
*
* @brief
* Return the threshold of switching to P4_* instead of P16_* for PRT resources
***************************************************************************************************
*/
-UINT_32 CIAddrLib::GetPrtSwitchP4Threshold() const
+UINT_32 CiAddrLib::GetPrtSwitchP4Threshold() const
{
UINT_32 threshold;
switch (m_pipes)
{
case 8:
threshold = 32;
break;
case 16:
if (m_settings.isFiji)
@@ -939,27 +939,27 @@ UINT_32 CIAddrLib::GetPrtSwitchP4Threshold() const
ADDR_ASSERT_ALWAYS();
threshold = 32;
break;
}
return threshold;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlSetupTileInfo
+* CiAddrLib::HwlSetupTileInfo
*
* @brief
* Setup default value of tile info for SI
***************************************************************************************************
*/
-VOID CIAddrLib::HwlSetupTileInfo(
+VOID CiAddrLib::HwlSetupTileInfo(
AddrTileMode tileMode, ///< [in] Tile mode
ADDR_SURFACE_FLAGS flags, ///< [in] Surface type flags
UINT_32 bpp, ///< [in] Bits per pixel
UINT_32 pitch, ///< [in] Pitch in pixels
UINT_32 height, ///< [in] Height in pixels
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
AddrTileType inTileType, ///< [in] Tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
@@ -1212,29 +1212,29 @@ VOID CIAddrLib::HwlSetupTileInfo(
}
else if (tileMode == ADDR_TM_LINEAR_ALIGNED)
{
pOut->tileIndex = 8;
*pTileInfo = m_tileTable[8].info;
}
}
/**
***************************************************************************************************
-* CIAddrLib::ReadGbTileMode
+* CiAddrLib::ReadGbTileMode
*
* @brief
* Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG.
* @return
* NA.
***************************************************************************************************
*/
-VOID CIAddrLib::ReadGbTileMode(
+VOID CiAddrLib::ReadGbTileMode(
UINT_32 regValue, ///< [in] GB_TILE_MODE register
ADDR_TILECONFIG* pCfg ///< [out] output structure
) const
{
GB_TILE_MODE gbTileMode;
gbTileMode.val = regValue;
pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode_new);
pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
@@ -1288,29 +1288,29 @@ VOID CIAddrLib::ReadGbTileMode(
pCfg->info.banks = 2;
pCfg->info.bankWidth = 1;
pCfg->info.bankHeight = 1;
pCfg->info.macroAspectRatio = 1;
pCfg->info.tileSplitBytes = 64;
}
}
/**
***************************************************************************************************
-* CIAddrLib::InitTileSettingTable
+* CiAddrLib::InitTileSettingTable
*
* @brief
* Initialize the ADDR_TILE_CONFIG table.
* @return
* TRUE if tile table is correctly initialized
***************************************************************************************************
*/
-BOOL_32 CIAddrLib::InitTileSettingTable(
+BOOL_32 CiAddrLib::InitTileSettingTable(
const UINT_32* pCfg, ///< [in] Pointer to table of tile configs
UINT_32 noOfEntries ///< [in] Numbe of entries in the table above
)
{
BOOL_32 initOk = TRUE;
ADDR_ASSERT(noOfEntries <= TileTableSize);
memset(m_tileTable, 0, sizeof(m_tileTable));
@@ -1357,53 +1357,53 @@ BOOL_32 CIAddrLib::InitTileSettingTable(
// Assume the first entry is always programmed with full pipes
m_pipes = HwlGetPipes(&m_tileTable[0].info);
}
return initOk;
}
/**
***************************************************************************************************
-* CIAddrLib::ReadGbMacroTileCfg
+* CiAddrLib::ReadGbMacroTileCfg
*
* @brief
* Convert GB_MACRO_TILE_CFG HW value to ADDR_TILE_CONFIG.
* @return
* NA.
***************************************************************************************************
*/
-VOID CIAddrLib::ReadGbMacroTileCfg(
+VOID CiAddrLib::ReadGbMacroTileCfg(
UINT_32 regValue, ///< [in] GB_MACRO_TILE_MODE register
ADDR_TILEINFO* pCfg ///< [out] output structure
) const
{
GB_MACROTILE_MODE gbTileMode;
gbTileMode.val = regValue;
pCfg->bankHeight = 1 << gbTileMode.f.bank_height;
pCfg->bankWidth = 1 << gbTileMode.f.bank_width;
pCfg->banks = 1 << (gbTileMode.f.num_banks + 1);
pCfg->macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
}
/**
***************************************************************************************************
-* CIAddrLib::InitMacroTileCfgTable
+* CiAddrLib::InitMacroTileCfgTable
*
* @brief
* Initialize the ADDR_MACRO_TILE_CONFIG table.
* @return
* TRUE if macro tile table is correctly initialized
***************************************************************************************************
*/
-BOOL_32 CIAddrLib::InitMacroTileCfgTable(
+BOOL_32 CiAddrLib::InitMacroTileCfgTable(
const UINT_32* pCfg, ///< [in] Pointer to table of tile configs
UINT_32 noOfMacroEntries ///< [in] Numbe of entries in the table above
)
{
BOOL_32 initOk = TRUE;
ADDR_ASSERT(noOfMacroEntries <= MacroTileTableSize);
memset(m_macroTileTable, 0, sizeof(m_macroTileTable));
@@ -1428,29 +1428,29 @@ BOOL_32 CIAddrLib::InitMacroTileCfgTable(
else
{
ADDR_ASSERT_ALWAYS();
initOk = FALSE;
}
return initOk;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeMacroModeIndex
+* CiAddrLib::HwlComputeMacroModeIndex
*
* @brief
* Computes macro tile mode index
* @return
* TRUE if macro tile table is correctly initialized
***************************************************************************************************
*/
-INT_32 CIAddrLib::HwlComputeMacroModeIndex(
+INT_32 CiAddrLib::HwlComputeMacroModeIndex(
INT_32 tileIndex, ///< [in] Tile mode index
ADDR_SURFACE_FLAGS flags, ///< [in] Surface flags
UINT_32 bpp, ///< [in] Bit per pixel
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfo, ///< [out] Pointer to ADDR_TILEINFO
AddrTileMode* pTileMode, ///< [out] Pointer to AddrTileMode
AddrTileType* pTileType ///< [out] Pointer to AddrTileType
) const
{
INT_32 macroModeIndex = TileIndexInvalid;
@@ -1543,33 +1543,33 @@ INT_32 CIAddrLib::HwlComputeMacroModeIndex(
{
*pTileType = tileType;
}
}
return macroModeIndex;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeTileDataWidthAndHeightLinear
+* CiAddrLib::HwlComputeTileDataWidthAndHeightLinear
*
* @brief
* Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
*
* @return
* N/A
*
* @note
* MacroWidth and macroHeight are measured in pixels
***************************************************************************************************
*/
-VOID CIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
+VOID CiAddrLib::HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, ///< [out] macro tile width
UINT_32* pMacroHeight, ///< [out] macro tile height
UINT_32 bpp, ///< [in] bits per pixel
ADDR_TILEINFO* pTileInfo ///< [in] tile info
) const
{
ADDR_ASSERT(pTileInfo != NULL);
UINT_32 numTiles;
@@ -1588,72 +1588,72 @@ VOID CIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
numTiles = 4;
break;
}
*pMacroWidth = numTiles * MicroTileWidth;
*pMacroHeight = numTiles * MicroTileHeight;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlStereoCheckRightOffsetPadding
+* CiAddrLib::HwlStereoCheckRightOffsetPadding
*
* @brief
* check if the height needs extra padding for stereo right eye offset, to avoid swizzling
*
* @return
* TRUE is the extra padding is needed
*
* @note
* Kalindi (Kabini) is the only one that needs this padding as there is a uncertain
* possible HW issue where the right eye displays incorrectly with some type of swizzles, if
* the right eye offset is not 64KB aligned - EPR#366461
* Other Kaveri APUs also need the padding according to DXX team's report otherwise
* corruption observed. - EPR#374788
***************************************************************************************************
*/
-BOOL_32 CIAddrLib::HwlStereoCheckRightOffsetPadding() const
+BOOL_32 CiAddrLib::HwlStereoCheckRightOffsetPadding() const
{
BOOL_32 bNeedPadding = FALSE;
if (m_settings.isKaveri)
{
bNeedPadding = TRUE;
}
return bNeedPadding;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlComputeMetadataNibbleAddress
+* CiAddrLib::HwlComputeMetadataNibbleAddress
*
* @brief
* calculate meta data address based on input information
*
* ¶meter
* uncompressedDataByteAddress - address of a pixel in color surface
* dataBaseByteAddress - base address of color surface
* metadataBaseByteAddress - base address of meta ram
* metadataBitSize - meta key size, 8 for DCC, 4 for cmask
* elementBitSize - element size of color surface
* blockByteSize - compression block size, 256 for DCC
* pipeInterleaveBytes - pipe interleave size
* numOfPipes - number of pipes
* numOfBanks - number of banks
* numOfSamplesPerSplit - number of samples per tile split
* @return
* meta data nibble address (nibble address is used to support DCC compatible cmask)
*
***************************************************************************************************
*/
-UINT_64 CIAddrLib::HwlComputeMetadataNibbleAddress(
+UINT_64 CiAddrLib::HwlComputeMetadataNibbleAddress(
UINT_64 uncompressedDataByteAddress,
UINT_64 dataBaseByteAddress,
UINT_64 metadataBaseByteAddress,
UINT_32 metadataBitSize,
UINT_32 elementBitSize,
UINT_32 blockByteSize,
UINT_32 pipeInterleaveBytes,
UINT_32 numOfPipes,
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const
@@ -1739,31 +1739,31 @@ UINT_64 CIAddrLib::HwlComputeMetadataNibbleAddress(
///--------------------------------------------------------------------------------------------
lsb = pipeInterleaveBits + 1; ///<+1 due to Nibble address now gives interleave bits extra lsb.
msb = pipeBits - 1 + lsb;
UINT_64 metadataAddress = AddrInsertBits(metaAddressInPipe, pipeDataBits, msb, lsb);
return metadataAddress;
}
/**
***************************************************************************************************
-* CIAddrLib::HwlPadDimensions
+* CiAddrLib::HwlPadDimensions
*
* @brief
* Helper function to pad dimensions
*
* @return
* N/A
*
***************************************************************************************************
*/
-VOID CIAddrLib::HwlPadDimensions(
+VOID CiAddrLib::HwlPadDimensions(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
ADDR_TILEINFO* pTileInfo, ///< [in/out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
UINT_32* pPitch, ///< [in/out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pHeight, ///< [in/out] height in pixels
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 2c9a4cc..05e9eda 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file ciaddrlib.h
-* @brief Contains the CIAddrLib class definition.
+* @brief Contains the CiAddrLib class definition.
***************************************************************************************************
*/
#ifndef __CI_ADDR_LIB_H__
#define __CI_ADDR_LIB_H__
#include "addrlib.h"
#include "siaddrlib.h"
/**
@@ -67,32 +67,32 @@ struct CIChipSettings
UINT_32 isCarrizo : 1;
};
};
/**
***************************************************************************************************
* @brief This class is the CI specific address library
* function set.
***************************************************************************************************
*/
-class CIAddrLib : public SIAddrLib
+class CiAddrLib : public SiAddrLib
{
public:
- /// Creates CIAddrLib object
+ /// Creates CiAddrLib object
static AddrLib* CreateObj(const AddrClient* pClient)
{
- return new(pClient) CIAddrLib(pClient);
+ return new(pClient) CiAddrLib(pClient);
}
private:
- CIAddrLib(const AddrClient* pClient);
- virtual ~CIAddrLib();
+ CiAddrLib(const AddrClient* pClient);
+ virtual ~CiAddrLib();
protected:
// Hwl interface - defined in AddrLib
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index a858b55..902e9f2 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -20,21 +20,21 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file siaddrlib.cpp
-* @brief Contains the implementation for the SIAddrLib class.
+* @brief Contains the implementation for the SiAddrLib class.
***************************************************************************************************
*/
#include "siaddrlib.h"
#include "si_gb_reg.h"
#include "si_ci_vi_merged_enum.h"
#if BRAHMA_BUILD
@@ -44,99 +44,99 @@
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
/**
***************************************************************************************************
* AddrSIHwlInit
*
* @brief
-* Creates an SIAddrLib object.
+* Creates an SiAddrLib object.
*
* @return
-* Returns an SIAddrLib object pointer.
+* Returns an SiAddrLib object pointer.
***************************************************************************************************
*/
AddrLib* AddrSIHwlInit(const AddrClient* pClient)
{
- return SIAddrLib::CreateObj(pClient);
+ return SiAddrLib::CreateObj(pClient);
}
/**
***************************************************************************************************
-* SIAddrLib::SIAddrLib
+* SiAddrLib::SiAddrLib
*
* @brief
* Constructor
*
***************************************************************************************************
*/
-SIAddrLib::SIAddrLib(const AddrClient* pClient) :
+SiAddrLib::SiAddrLib(const AddrClient* pClient) :
EgBasedAddrLib(pClient),
m_noOfEntries(0)
{
m_class = SI_ADDRLIB;
memset(&m_settings, 0, sizeof(m_settings));
}
/**
***************************************************************************************************
-* SIAddrLib::~SIAddrLib
+* SiAddrLib::~SiAddrLib
*
* @brief
* Destructor
***************************************************************************************************
*/
-SIAddrLib::~SIAddrLib()
+SiAddrLib::~SiAddrLib()
{
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetPipes
+* SiAddrLib::HwlGetPipes
*
* @brief
* Get number pipes
* @return
* num pipes
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlGetPipes(
+UINT_32 SiAddrLib::HwlGetPipes(
const ADDR_TILEINFO* pTileInfo ///< [in] Tile info
) const
{
UINT_32 numPipes;
if (pTileInfo)
{
numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
}
else
{
ADDR_ASSERT_ALWAYS();
numPipes = m_pipes; // Suppose we should still have a global pipes
}
return numPipes;
}
/**
***************************************************************************************************
-* SIAddrLib::GetPipePerSurf
+* SiAddrLib::GetPipePerSurf
* @brief
* get pipe num base on inputing tileinfo->pipeconfig
* @return
* pipe number
***************************************************************************************************
*/
-UINT_32 SIAddrLib::GetPipePerSurf(
+UINT_32 SiAddrLib::GetPipePerSurf(
AddrPipeCfg pipeConfig ///< [in] pipe config
) const
{
UINT_32 numPipes = 0;
switch (pipeConfig)
{
case ADDR_PIPECFG_P2:
numPipes = 2;
break;
@@ -161,29 +161,29 @@ UINT_32 SIAddrLib::GetPipePerSurf(
break;
default:
ADDR_ASSERT(!"Invalid pipe config");
numPipes = m_pipes;
}
return numPipes;
}
/**
***************************************************************************************************
-* SIAddrLib::ComputePipeFromCoord
+* SiAddrLib::ComputePipeFromCoord
*
* @brief
* Compute pipe number from coordinates
* @return
* Pipe number
***************************************************************************************************
*/
-UINT_32 SIAddrLib::ComputePipeFromCoord(
+UINT_32 SiAddrLib::ComputePipeFromCoord(
UINT_32 x, ///< [in] x coordinate
UINT_32 y, ///< [in] y coordinate
UINT_32 slice, ///< [in] slice index
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 pipeSwizzle, ///< [in] pipe swizzle
BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
ADDR_TILEINFO* pTileInfo ///< [in] Tile info
) const
{
UINT_32 pipe;
@@ -312,29 +312,29 @@ UINT_32 SIAddrLib::ComputePipeFromCoord(
pipeSwizzle += sliceRotation;
pipeSwizzle &= (numPipes - 1);
pipe = pipe ^ pipeSwizzle;
return pipe;
}
/**
***************************************************************************************************
-* SIAddrLib::ComputeTileCoordFromPipeAndElemIdx
+* SiAddrLib::ComputeTileCoordFromPipeAndElemIdx
*
* @brief
* Compute (x,y) of a tile within a macro tile from address
* @return
* Pipe number
***************************************************************************************************
*/
-VOID SIAddrLib::ComputeTileCoordFromPipeAndElemIdx(
+VOID SiAddrLib::ComputeTileCoordFromPipeAndElemIdx(
UINT_32 elemIdx, ///< [in] per pipe element index within a macro tile
UINT_32 pipe, ///< [in] pipe index
AddrPipeCfg pipeCfg, ///< [in] pipe config
UINT_32 pitchInMacroTile, ///< [in] surface pitch in macro tile
UINT_32 x, ///< [in] x coordinate of the (0,0) tile in a macro tile
UINT_32 y, ///< [in] y coordinate of the (0,0) tile in a macro tile
UINT_32* pX, ///< [out] x coordinate
UINT_32* pY ///< [out] y coordinate
) const
{
@@ -569,29 +569,29 @@ VOID SIAddrLib::ComputeTileCoordFromPipeAndElemIdx(
*pX = Bits2Number(3, x5, x4, x3);
}
break;
default:
ADDR_UNHANDLED_CASE();
}
}
/**
***************************************************************************************************
-* SIAddrLib::TileCoordToMaskElementIndex
+* SiAddrLib::TileCoordToMaskElementIndex
*
* @brief
* Compute element index from coordinates in tiles
* @return
* Element index
***************************************************************************************************
*/
-UINT_32 SIAddrLib::TileCoordToMaskElementIndex(
+UINT_32 SiAddrLib::TileCoordToMaskElementIndex(
UINT_32 tx, ///< [in] x coord, in Tiles
UINT_32 ty, ///< [in] y coord, in Tiles
AddrPipeCfg pipeConfig, ///< [in] pipe config
UINT_32* macroShift, ///< [out] macro shift
UINT_32* elemIdxBits ///< [out] tile offset bits
) const
{
UINT_32 elemIdx = 0;
UINT_32 elemIdx0, elemIdx1, elemIdx2;
UINT_32 tx0, tx1;
@@ -705,33 +705,33 @@ UINT_32 SIAddrLib::TileCoordToMaskElementIndex(
default:
ADDR_UNHANDLED_CASE();
break;
}
return elemIdx;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeTileDataWidthAndHeightLinear
+* SiAddrLib::HwlComputeTileDataWidthAndHeightLinear
*
* @brief
* Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
*
* @return
* N/A
*
* @note
* MacroWidth and macroHeight are measured in pixels
***************************************************************************************************
*/
-VOID SIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
+VOID SiAddrLib::HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, ///< [out] macro tile width
UINT_32* pMacroHeight, ///< [out] macro tile height
UINT_32 bpp, ///< [in] bits per pixel
ADDR_TILEINFO* pTileInfo ///< [in] tile info
) const
{
ADDR_ASSERT(pTileInfo != NULL);
UINT_32 macroWidth;
UINT_32 macroHeight;
@@ -751,53 +751,53 @@ VOID SIAddrLib::HwlComputeTileDataWidthAndHeightLinear(
macroWidth = 4*MicroTileWidth;
macroHeight = 4*MicroTileHeight;
}
*pMacroWidth = macroWidth;
*pMacroHeight = macroHeight;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeHtileBytes
+* SiAddrLib::HwlComputeHtileBytes
*
* @brief
* Compute htile size in bytes
*
* @return
* Htile size in bytes
***************************************************************************************************
*/
-UINT_64 SIAddrLib::HwlComputeHtileBytes(
+UINT_64 SiAddrLib::HwlComputeHtileBytes(
UINT_32 pitch, ///< [in] pitch
UINT_32 height, ///< [in] height
UINT_32 bpp, ///< [in] bits per pixel
BOOL_32 isLinear, ///< [in] if it is linear mode
UINT_32 numSlices, ///< [in] number of slices
UINT_64* pSliceBytes, ///< [out] bytes per slice
UINT_32 baseAlign ///< [in] base alignments
) const
{
return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeXmaskAddrFromCoord
+* SiAddrLib::HwlComputeXmaskAddrFromCoord
*
* @brief
* Compute address from coordinates for htile/cmask
* @return
* Byte address
***************************************************************************************************
*/
-UINT_64 SIAddrLib::HwlComputeXmaskAddrFromCoord(
+UINT_64 SiAddrLib::HwlComputeXmaskAddrFromCoord(
UINT_32 pitch, ///< [in] pitch
UINT_32 height, ///< [in] height
UINT_32 x, ///< [in] x coord
UINT_32 y, ///< [in] y coord
UINT_32 slice, ///< [in] slice/depth index
UINT_32 numSlices, ///< [in] number of slices
UINT_32 factor, ///< [in] factor that indicates cmask(2) or htile(1)
BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
BOOL_32 isWidth8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
BOOL_32 isHeight8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
@@ -930,33 +930,33 @@ UINT_64 SIAddrLib::HwlComputeXmaskAddrFromCoord(
pipe * (m_pipeInterleaveBytes * 8) +
totalOffset / (m_pipeInterleaveBytes * 8) * (m_pipeInterleaveBytes * 8) * numPipes;
*pBitPosition = static_cast<UINT_32>(addrInBits) % 8;
UINT_64 addr = addrInBits / 8;
return addr;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeXmaskCoordFromAddr
+* SiAddrLib::HwlComputeXmaskCoordFromAddr
*
* @brief
* Compute the coord from an address of a cmask/htile
*
* @return
* N/A
*
* @note
* This method is reused by htile, so rename to Xmask
***************************************************************************************************
*/
-VOID SIAddrLib::HwlComputeXmaskCoordFromAddr(
+VOID SiAddrLib::HwlComputeXmaskCoordFromAddr(
UINT_64 addr, ///< [in] address
UINT_32 bitPosition, ///< [in] bitPosition in a byte
UINT_32 pitch, ///< [in] pitch
UINT_32 height, ///< [in] height
UINT_32 numSlices, ///< [in] number of slices
UINT_32 factor, ///< [in] factor that indicates cmask or htile
BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
BOOL_32 isWidth8, ///< [in] Not used by SI
BOOL_32 isHeight8, ///< [in] Not used by SI
ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
@@ -1136,28 +1136,28 @@ VOID SIAddrLib::HwlComputeXmaskCoordFromAddr(
UINT_32 microY;
ComputeTileCoordFromPipeAndElemIdx(elemIdx, pipe, pTileInfo->pipeConfig, pitchInMacroTile,
*pX, *pY, µX, µY);
*pX += microX * MicroTileWidth;
*pY += microY * MicroTileWidth;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetPitchAlignmentLinear
+* SiAddrLib::HwlGetPitchAlignmentLinear
* @brief
* Get pitch alignment
* @return
* pitch alignment
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlGetPitchAlignmentLinear(
+UINT_32 SiAddrLib::HwlGetPitchAlignmentLinear(
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags ///< [in] surface flags
) const
{
UINT_32 pitchAlign;
// Interleaved access requires a 256B aligned pitch, so fall back to pre-SI alignment
if (flags.interleaved)
{
pitchAlign = Max(64u, m_pipeInterleaveBytes / BITS_TO_BYTES(bpp));
@@ -1166,30 +1166,30 @@ UINT_32 SIAddrLib::HwlGetPitchAlignmentLinear(
else
{
pitchAlign = Max(8u, 64 / BITS_TO_BYTES(bpp));
}
return pitchAlign;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetSizeAdjustmentLinear
+* SiAddrLib::HwlGetSizeAdjustmentLinear
*
* @brief
* Adjust linear surface pitch and slice size
*
* @return
* Logical slice size in bytes
***************************************************************************************************
*/
-UINT_64 SIAddrLib::HwlGetSizeAdjustmentLinear(
+UINT_64 SiAddrLib::HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pPitch, ///< [in/out] pointer to pitch
UINT_32* pHeight, ///< [in/out] pointer to height
UINT_32* pHeightAlign ///< [in/out] pointer to height align
) const
{
@@ -1227,30 +1227,30 @@ UINT_64 SIAddrLib::HwlGetSizeAdjustmentLinear(
*pHeightAlign = heightAlign;
sliceSize = BITS_TO_BYTES(pixelPerSlice * bpp);
}
return sliceSize;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlPreHandleBaseLvl3xPitch
+* SiAddrLib::HwlPreHandleBaseLvl3xPitch
*
* @brief
* Pre-handler of 3x pitch (96 bit) adjustment
*
* @return
* Expected pitch
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlPreHandleBaseLvl3xPitch(
+UINT_32 SiAddrLib::HwlPreHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
UINT_32 expPitch ///< [in] pitch
) const
{
ADDR_ASSERT(pIn->width == expPitch);
// From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
// do here
if (!pIn->flags.pow2Pad)
{
@@ -1259,59 +1259,59 @@ UINT_32 SIAddrLib::HwlPreHandleBaseLvl3xPitch(
else
{
ADDR_ASSERT(IsPow2(expPitch));
}
return expPitch;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlPostHandleBaseLvl3xPitch
+* SiAddrLib::HwlPostHandleBaseLvl3xPitch
*
* @brief
* Post-handler of 3x pitch adjustment
*
* @return
* Expected pitch
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlPostHandleBaseLvl3xPitch(
+UINT_32 SiAddrLib::HwlPostHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
UINT_32 expPitch ///< [in] pitch
) const
{
/**
* @note The pitch will be divided by 3 in the end so the value will look odd but h/w should
* be able to compute a correct pitch from it as h/w address library is doing the job.
*/
// From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
if (!pIn->flags.pow2Pad)
{
AddrLib::HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
}
return expPitch;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetPitchAlignmentMicroTiled
+* SiAddrLib::HwlGetPitchAlignmentMicroTiled
*
* @brief
* Compute 1D tiled surface pitch alignment
*
* @return
* pitch alignment
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlGetPitchAlignmentMicroTiled(
+UINT_32 SiAddrLib::HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples ///< [in] number of samples
) const
{
UINT_32 pitchAlign;
if (flags.qbStereo)
{
@@ -1320,30 +1320,30 @@ UINT_32 SIAddrLib::HwlGetPitchAlignmentMicroTiled(
else
{
pitchAlign = 8;
}
return pitchAlign;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetSizeAdjustmentMicroTiled
+* SiAddrLib::HwlGetSizeAdjustmentMicroTiled
*
* @brief
* Adjust 1D tiled surface pitch and slice size
*
* @return
* Logical slice size in bytes
***************************************************************************************************
*/
-UINT_64 SIAddrLib::HwlGetSizeAdjustmentMicroTiled(
+UINT_64 SiAddrLib::HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, ///< [in] thickness
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
UINT_32 baseAlign, ///< [in] base alignment
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pPitch, ///< [in/out] pointer to pitch
UINT_32* pHeight ///< [in/out] pointer to height
) const
{
@@ -1400,29 +1400,29 @@ UINT_64 SIAddrLib::HwlGetSizeAdjustmentMicroTiled(
#endif
*pPitch = pitch;
// No adjust for pHeight
return logicalSliceSize;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlConvertChipFamily
+* SiAddrLib::HwlConvertChipFamily
*
* @brief
* Convert familyID defined in atiid.h to AddrChipFamily and set m_chipFamily/m_chipRevision
* @return
* AddrChipFamily
***************************************************************************************************
*/
-AddrChipFamily SIAddrLib::HwlConvertChipFamily(
+AddrChipFamily SiAddrLib::HwlConvertChipFamily(
UINT_32 uChipFamily, ///< [in] chip family defined in atiih.h
UINT_32 uChipRevision) ///< [in] chip revision defined in "asic_family"_id.h
{
AddrChipFamily family = ADDR_CHIP_FAMILY_SI;
switch (uChipFamily)
{
case FAMILY_SI:
m_settings.isSouthernIsland = 1;
m_settings.isTahiti = ASICREV_IS_TAHITI_P(uChipRevision);
@@ -1434,27 +1434,27 @@ AddrChipFamily SIAddrLib::HwlConvertChipFamily(
default:
ADDR_ASSERT(!"This should be a Fusion");
break;
}
return family;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlSetupTileInfo
+* SiAddrLib::HwlSetupTileInfo
*
* @brief
* Setup default value of tile info for SI
***************************************************************************************************
*/
-VOID SIAddrLib::HwlSetupTileInfo(
+VOID SiAddrLib::HwlSetupTileInfo(
AddrTileMode tileMode, ///< [in] Tile mode
ADDR_SURFACE_FLAGS flags, ///< [in] Surface type flags
UINT_32 bpp, ///< [in] Bits per pixel
UINT_32 pitch, ///< [in] Pitch in pixels
UINT_32 height, ///< [in] Height in pixels
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
AddrTileType inTileType, ///< [in] Tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
@@ -1757,31 +1757,31 @@ VOID SIAddrLib::HwlSetupTileInfo(
}
// Pass through tile type
pOut->tileType = inTileType;
}
pOut->tileIndex = index;
}
/**
***************************************************************************************************
-* SIAddrLib::DecodeGbRegs
+* SiAddrLib::DecodeGbRegs
*
* @brief
* Decodes GB_ADDR_CONFIG and noOfBanks/noOfRanks
*
* @return
* TRUE if all settings are valid
*
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::DecodeGbRegs(
+BOOL_32 SiAddrLib::DecodeGbRegs(
const ADDR_REGISTER_VALUE* pRegValue) ///< [in] create input
{
GB_ADDR_CONFIG reg;
BOOL_32 valid = TRUE;
reg.val = pRegValue->gbAddrConfig;
switch (reg.f.pipe_interleave_size)
{
case ADDR_CONFIG_PIPE_INTERLEAVE_256B:
@@ -1846,31 +1846,31 @@ BOOL_32 SIAddrLib::DecodeGbRegs(
m_logicalBanks = m_banks * m_ranks;
ADDR_ASSERT(m_logicalBanks <= 16);
return valid;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlInitGlobalParams
+* SiAddrLib::HwlInitGlobalParams
*
* @brief
* Initializes global parameters
*
* @return
* TRUE if all settings are valid
*
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::HwlInitGlobalParams(
+BOOL_32 SiAddrLib::HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
{
BOOL_32 valid = TRUE;
const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
valid = DecodeGbRegs(pRegValue);
if (valid)
{
if (m_settings.isTahiti || m_settings.isPitCairn)
@@ -1890,28 +1890,28 @@ BOOL_32 SIAddrLib::HwlInitGlobalParams(
valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
m_maxSamples = 16;
}
return valid;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlConvertTileInfoToHW
+* SiAddrLib::HwlConvertTileInfoToHW
* @brief
* Entry of si's ConvertTileInfoToHW
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE SIAddrLib::HwlConvertTileInfoToHW(
+ADDR_E_RETURNCODE SiAddrLib::HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE retCode = ADDR_OK;
retCode = EgBasedAddrLib::HwlConvertTileInfoToHW(pIn, pOut);
if (retCode == ADDR_OK)
{
@@ -1932,52 +1932,52 @@ ADDR_E_RETURNCODE SIAddrLib::HwlConvertTileInfoToHW(
pOut->pTileInfo->pipeConfig =
static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig + 1);
}
}
return retCode;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeXmaskCoordYFrom8Pipe
+* SiAddrLib::HwlComputeXmaskCoordYFrom8Pipe
*
* @brief
* Compute the Y coord which will be added to Xmask Y
* coord.
* @return
* Y coord
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlComputeXmaskCoordYFrom8Pipe(
+UINT_32 SiAddrLib::HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, ///< [in] pipe id
UINT_32 x ///< [in] tile coord x, which is original x coord / 8
) const
{
// This function should never be called since it is 6xx/8xx specfic.
// Keep this empty implementation to avoid any mis-use.
ADDR_ASSERT_ALWAYS();
return 0;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe
+* SiAddrLib::HwlComputeSurfaceCoord2DFromBankPipe
*
* @brief
* Compute surface x,y coordinates from bank/pipe info
* @return
* N/A
***************************************************************************************************
*/
-VOID SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe(
+VOID SiAddrLib::HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32* pX, ///< [in/out] x coordinate
UINT_32* pY, ///< [in/out] y coordinate
UINT_32 slice, ///< [in] slice index
UINT_32 bank, ///< [in] bank number
UINT_32 pipe, ///< [in] pipe number
UINT_32 bankSwizzle,///< [in] bank swizzle
UINT_32 pipeSwizzle,///< [in] pipe swizzle
UINT_32 tileSlices, ///< [in] slices in a micro tile
BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
@@ -2120,29 +2120,29 @@ VOID SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe(
ADDR_ASSERT_ALWAYS();
}
xTile = Bits2Number(3, x5, x4, x3);
*pX += xTile << 3;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlPreAdjustBank
+* SiAddrLib::HwlPreAdjustBank
*
* @brief
* Adjust bank before calculating address acoording to bank/pipe
* @return
* Adjusted bank
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlPreAdjustBank(
+UINT_32 SiAddrLib::HwlPreAdjustBank(
UINT_32 tileX, ///< [in] x coordinate in unit of tile
UINT_32 bank, ///< [in] bank
ADDR_TILEINFO* pTileInfo ///< [in] tile info
) const
{
if (((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
(pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
{
UINT_32 bankBit0 = _BIT(bank, 0);
UINT_32 x4 = _BIT(tileX, 1);
@@ -2152,48 +2152,48 @@ UINT_32 SIAddrLib::HwlPreAdjustBank(
bank |= bankBit0;
ADDR_ASSERT(pTileInfo->macroAspectRatio > 1)
}
return bank;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeSurfaceInfo
+* SiAddrLib::HwlComputeSurfaceInfo
*
* @brief
* Entry of si's ComputeSurfaceInfo
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE SIAddrLib::HwlComputeSurfaceInfo(
+ADDR_E_RETURNCODE SiAddrLib::HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
) const
{
pOut->tileIndex = pIn->tileIndex;
return EgBasedAddrLib::HwlComputeSurfaceInfo(pIn,pOut);
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeMipLevel
+* SiAddrLib::HwlComputeMipLevel
* @brief
* Compute MipLevel info (including level 0)
* @return
* TRUE if HWL's handled
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::HwlComputeMipLevel(
+BOOL_32 SiAddrLib::HwlComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
) const
{
// basePitch is calculated from level 0 so we only check this for mipLevel > 0
if (pIn->mipLevel > 0)
{
// Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
// we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
// divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
if (!AddrElemLib::IsExpand3x(pIn->format))
@@ -2209,29 +2209,29 @@ BOOL_32 SIAddrLib::HwlComputeMipLevel(
}
}
// pow2Pad is done in PostComputeMipLevel
return TRUE;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlCheckLastMacroTiledLvl
+* SiAddrLib::HwlCheckLastMacroTiledLvl
*
* @brief
* Sets pOut->last2DLevel to TRUE if it is
* @note
*
***************************************************************************************************
*/
-VOID SIAddrLib::HwlCheckLastMacroTiledLvl(
+VOID SiAddrLib::HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in/out] Output structure (used as input, too)
) const
{
// pow2Pad covers all mipmap cases
if (pIn->flags.pow2Pad)
{
ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
UINT_32 nextPitch;
@@ -2284,93 +2284,93 @@ VOID SIAddrLib::HwlCheckLastMacroTiledLvl(
pOut->pitchAlign,
pOut->heightAlign,
pOut->pTileInfo);
pOut->last2DLevel = IsMicroTiled(nextTileMode);
}
}
/**
***************************************************************************************************
-* SIAddrLib::HwlDegradeThickTileMode
+* SiAddrLib::HwlDegradeThickTileMode
*
* @brief
* Degrades valid tile mode for thick modes if needed
*
* @return
* Suitable tile mode
***************************************************************************************************
*/
-AddrTileMode SIAddrLib::HwlDegradeThickTileMode(
+AddrTileMode SiAddrLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
) const
{
return EgBasedAddrLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
}
/**
***************************************************************************************************
-* SIAddrLib::HwlTileInfoEqual
+* SiAddrLib::HwlTileInfoEqual
*
* @brief
* Return TRUE if all field are equal
* @note
* Only takes care of current HWL's data
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::HwlTileInfoEqual(
+BOOL_32 SiAddrLib::HwlTileInfoEqual(
const ADDR_TILEINFO* pLeft, ///<[in] Left compare operand
const ADDR_TILEINFO* pRight ///<[in] Right compare operand
) const
{
BOOL_32 equal = FALSE;
if (pLeft->pipeConfig == pRight->pipeConfig)
{
equal = EgBasedAddrLib::HwlTileInfoEqual(pLeft, pRight);
}
return equal;
}
/**
***************************************************************************************************
-* SIAddrLib::GetTileSettings
+* SiAddrLib::GetTileSettings
*
* @brief
* Get tile setting infos by index.
* @return
* Tile setting info.
***************************************************************************************************
*/
-const ADDR_TILECONFIG* SIAddrLib::GetTileSetting(
+const ADDR_TILECONFIG* SiAddrLib::GetTileSetting(
UINT_32 index ///< [in] Tile index
) const
{
ADDR_ASSERT(index < m_noOfEntries);
return &m_tileTable[index];
}
/**
***************************************************************************************************
-* SIAddrLib::HwlPostCheckTileIndex
+* SiAddrLib::HwlPostCheckTileIndex
*
* @brief
* Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
* tile mode/type/info and change the index if needed
* @return
* Tile index.
***************************************************************************************************
*/
-INT_32 SIAddrLib::HwlPostCheckTileIndex(
+INT_32 SiAddrLib::HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, ///< [in] Tile Info
AddrTileMode mode, ///< [in] Tile mode
AddrTileType type, ///< [in] Tile type
INT curIndex ///< [in] Current index assigned in HwlSetupTileInfo
) const
{
INT_32 index = curIndex;
if (mode == ADDR_TM_LINEAR_GENERAL)
{
@@ -2426,29 +2426,29 @@ INT_32 SIAddrLib::HwlPostCheckTileIndex(
if (index >= static_cast<INT_32>(m_noOfEntries))
{
index = TileIndexInvalid;
}
return index;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlSetupTileCfg
+* SiAddrLib::HwlSetupTileCfg
*
* @brief
* Map tile index to tile setting.
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-ADDR_E_RETURNCODE SIAddrLib::HwlSetupTileCfg(
+ADDR_E_RETURNCODE SiAddrLib::HwlSetupTileCfg(
INT_32 index, ///< [in] Tile index
INT_32 macroModeIndex, ///< [in] Index in macro tile mode table(CI)
ADDR_TILEINFO* pInfo, ///< [out] Tile Info
AddrTileMode* pMode, ///< [out] Tile mode
AddrTileType* pType ///< [out] Tile type
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
// Global flag to control usage of tileIndex
@@ -2506,29 +2506,29 @@ ADDR_E_RETURNCODE SIAddrLib::HwlSetupTileCfg(
*pType = pCfgTable->type;
}
}
}
return returnCode;
}
/**
***************************************************************************************************
-* SIAddrLib::ReadGbTileMode
+* SiAddrLib::ReadGbTileMode
*
* @brief
* Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG.
* @return
* NA.
***************************************************************************************************
*/
-VOID SIAddrLib::ReadGbTileMode(
+VOID SiAddrLib::ReadGbTileMode(
UINT_32 regValue, ///< [in] GB_TILE_MODE register
ADDR_TILECONFIG* pCfg ///< [out] output structure
) const
{
GB_TILE_MODE gbTileMode;
gbTileMode.val = regValue;
pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
@@ -2546,29 +2546,29 @@ VOID SIAddrLib::ReadGbTileMode(
pCfg->mode = ADDR_TM_2D_TILED_XTHICK;
}
else if (regArrayMode >= 14) //ARRAY_3D_TILED_XTHICK
{
pCfg->mode = static_cast<AddrTileMode>(pCfg->mode + 3);
}
}
/**
***************************************************************************************************
-* SIAddrLib::InitTileSettingTable
+* SiAddrLib::InitTileSettingTable
*
* @brief
* Initialize the ADDR_TILE_CONFIG table.
* @return
* TRUE if tile table is correctly initialized
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::InitTileSettingTable(
+BOOL_32 SiAddrLib::InitTileSettingTable(
const UINT_32* pCfg, ///< [in] Pointer to table of tile configs
UINT_32 noOfEntries ///< [in] Numbe of entries in the table above
)
{
BOOL_32 initOk = TRUE;
ADDR_ASSERT(noOfEntries <= TileTableSize);
memset(m_tileTable, 0, sizeof(m_tileTable));
@@ -2597,88 +2597,88 @@ BOOL_32 SIAddrLib::InitTileSettingTable(
if (initOk)
{
ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
}
return initOk;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlGetTileIndex
+* SiAddrLib::HwlGetTileIndex
*
* @brief
* Return the virtual/real index for given mode/type/info
* @return
* ADDR_OK if successful.
***************************************************************************************************
*/
-ADDR_E_RETURNCODE SIAddrLib::HwlGetTileIndex(
+ADDR_E_RETURNCODE SiAddrLib::HwlGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
pOut->index = HwlPostCheckTileIndex(pIn->pTileInfo, pIn->tileMode, pIn->tileType);
return returnCode;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlFmaskPreThunkSurfInfo
+* SiAddrLib::HwlFmaskPreThunkSurfInfo
*
* @brief
* Some preparation before thunking a ComputeSurfaceInfo call for Fmask
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-VOID SIAddrLib::HwlFmaskPreThunkSurfInfo(
+VOID SiAddrLib::HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn, ///< [in] Input of fmask info
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut, ///< [in] Output of fmask info
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn, ///< [out] Input of thunked surface info
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut ///< [out] Output of thunked surface info
) const
{
pSurfIn->tileIndex = pFmaskIn->tileIndex;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlFmaskPostThunkSurfInfo
+* SiAddrLib::HwlFmaskPostThunkSurfInfo
*
* @brief
* Copy hwl extra field after calling thunked ComputeSurfaceInfo
* @return
* ADDR_E_RETURNCODE
***************************************************************************************************
*/
-VOID SIAddrLib::HwlFmaskPostThunkSurfInfo(
+VOID SiAddrLib::HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut, ///< [in] Output of surface info
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut ///< [out] Output of fmask info
) const
{
pFmaskOut->macroModeIndex = TileIndexInvalid;
pFmaskOut->tileIndex = pSurfOut->tileIndex;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlComputeFmaskBits
+* SiAddrLib::HwlComputeFmaskBits
* @brief
* Computes fmask bits
* @return
* Fmask bits
***************************************************************************************************
*/
-UINT_32 SIAddrLib::HwlComputeFmaskBits(
+UINT_32 SiAddrLib::HwlComputeFmaskBits(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
UINT_32* pNumSamples
) const
{
UINT_32 numSamples = pIn->numSamples;
UINT_32 numFrags = GetNumFragments(numSamples, pIn->numFrags);
UINT_32 bpp;
if (numFrags != numSamples) // EQAA
{
@@ -2758,31 +2758,31 @@ UINT_32 SIAddrLib::HwlComputeFmaskBits(
}
}
SafeAssign(pNumSamples, numSamples);
return bpp;
}
/**
***************************************************************************************************
-* SIAddrLib::HwlOverrideTileMode
+* SiAddrLib::HwlOverrideTileMode
*
* @brief
* Override tile modes (for PRT only, avoid client passes in an invalid PRT mode for SI.
*
* @return
* Suitable tile mode
*
***************************************************************************************************
*/
-BOOL_32 SIAddrLib::HwlOverrideTileMode(
+BOOL_32 SiAddrLib::HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
AddrTileMode* pTileMode, ///< [in/out] pointer to the tile mode
AddrTileType* pTileType ///< [in/out] pointer to the tile type
) const
{
BOOL_32 bOverrided = FALSE;
AddrTileMode tileMode = *pTileMode;
switch (tileMode)
{
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index 897beb1..034001a 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -67,32 +67,32 @@ struct SIChipSettings
UINT_32 isHainan : 1;
};
};
/**
***************************************************************************************************
* @brief This class is the SI specific address library
* function set.
***************************************************************************************************
*/
-class SIAddrLib : public EgBasedAddrLib
+class SiAddrLib : public EgBasedAddrLib
{
public:
/// Creates SIAddrLib object
static AddrLib* CreateObj(const AddrClient* pClient)
{
- return new(pClient) SIAddrLib(pClient);
+ return new(pClient) SiAddrLib(pClient);
}
protected:
- SIAddrLib(const AddrClient* pClient);
- virtual ~SIAddrLib();
+ SiAddrLib(const AddrClient* pClient);
+ virtual ~SiAddrLib();
// Hwl interface - defined in AddrLib
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
--
2.7.4
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