[Mesa-dev] [PATCH 029/140] amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled

Marek Olšák maraeo at gmail.com
Mon Mar 20 22:42:39 UTC 2017


From: Roy Zhan <roy.zhan at amd.com>

Experiment show 1D tiling + TcCompatible cannot work together.
---
 src/amd/addrlib/r800/ciaddrlib.cpp | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 3322d95..f88741e 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1310,44 +1310,47 @@ VOID CiAddrLib::HwlSetupTileInfo(
 
         // Copy linear-aligned entry??
         *pTileInfo = m_tileTable[8].info;
     }
     else if (tileMode == ADDR_TM_LINEAR_ALIGNED)
     {
         pOut->tileIndex = 8;
         *pTileInfo = m_tileTable[8].info;
     }
 
-    // Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil is
-    // handled at tileIndex selecting time.
-    if (pOut->tcCompatible && (inTileType != ADDR_DEPTH_SAMPLE_ORDER))
+    if (pOut->tcCompatible)
     {
         if (IsMacroTiled(tileMode))
         {
-            INT_32 tileIndex = pOut->tileIndex;
-
-            if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
+            if (inTileType != ADDR_DEPTH_SAMPLE_ORDER)
             {
-                tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
-            }
+                // Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
+                // tileSplit case was handled at tileIndex selecting time.
+                INT_32 tileIndex = pOut->tileIndex;
 
-            if (tileIndex != TileIndexInvalid)
-            {
-                ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
-                // Non-depth entries store a split factor
-                UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
-                UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
-                UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
+                if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
+                {
+                    tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
+                }
 
-                if (m_rowSize < colorTileSplit)
+                if (tileIndex != TileIndexInvalid)
                 {
-                    pOut->tcCompatible = FALSE;
+                    ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
+                    // Non-depth entries store a split factor
+                    UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
+                    UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
+                    UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
+
+                    if (m_rowSize < colorTileSplit)
+                    {
+                        pOut->tcCompatible = FALSE;
+                    }
                 }
             }
         }
         else
         {
             // Client should not enable tc compatible for linear and 1D tile modes.
             pOut->tcCompatible = FALSE;
         }
     }
 }
-- 
2.7.4



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