[Mesa-dev] [PATCH 015/140] amdgpu/addrlib: add dccRamSizeAligned output flag

[Marek Olšák]

From: Xavi Zhang <xavi.zhang at amd.com>

This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
---
 src/amd/addrlib/addrinterface.h    | 3 ++-
 src/amd/addrlib/r800/ciaddrlib.cpp | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index d94518f..bd10310 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -2121,21 +2121,22 @@ typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
 *   @brief
 *       Output structure of AddrComputeDccInfo
 ***************************************************************************************************
 */
 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
 {
     UINT_32 size;                 ///< Size of this structure in bytes
     UINT_64 dccRamBaseAlign;      ///< Base alignment of dcc key
     UINT_64 dccRamSize;           ///< Size of dcc key
     UINT_64 dccFastClearSize;     ///< Size of dcc key portion that can be fast cleared
-    BOOL_32 subLvlCompressible;   ///< whether sub resource is compressiable
+    BOOL_32 subLvlCompressible;   ///< Whether sub resource is compressiable
+    BOOL_32 dccRamSizeAligned;    ///< Whether the dcc key size is aligned
 } ADDR_COMPUTE_DCCINFO_OUTPUT;
 
 /**
 ***************************************************************************************************
 *   AddrComputeDccInfo
 *
 *   @brief
 *       Compute DCC key size, base alignment
 *       info
 ***************************************************************************************************
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 776c8b5..97ef3b6 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -240,35 +240,40 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
                     dccFastClearSize = 0;
                 }
             }
         }
 
         pOut->dccRamSize          = pIn->colorSurfSize >> 8;
         pOut->dccRamBaseAlign     = pIn->tileInfo.banks *
                                     HwlGetPipes(&pIn->tileInfo) *
                                     m_pipeInterleaveBytes;
         pOut->dccFastClearSize    = dccFastClearSize;
+        pOut->dccRamSizeAligned   = TRUE;
 
         ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
 
         if (0 == (pOut->dccRamSize & (pOut->dccRamBaseAlign - 1)))
         {
             pOut->subLvlCompressible = TRUE;
         }
         else
         {
             UINT_64 dccRamSizeAlign = HwlGetPipes(&pIn->tileInfo) * m_pipeInterleaveBytes;
 
             if (pOut->dccRamSize == pOut->dccFastClearSize)
             {
                 pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             }
+            if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
+            {
+                pOut->dccRamSizeAligned = FALSE;
+            }
             pOut->dccRamSize          = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             pOut->subLvlCompressible  = FALSE;
         }
     }
     else
     {
         returnCode = ADDR_NOTSUPPORTED;
     }
 
     return returnCode;
-- 
2.7.4