[Mesa-dev] [PATCH 025/140] amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:42:35 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
---
src/amd/addrlib/core/addrlib1.cpp | 16 ++++++++--------
src/amd/addrlib/core/addrlib1.h | 2 +-
src/amd/addrlib/r800/ciaddrlib.cpp | 8 ++++----
src/amd/addrlib/r800/egbaddrlib.cpp | 34 +++++++++++++++++-----------------
src/amd/addrlib/r800/siaddrlib.cpp | 4 ++--
5 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index 6895917..922455b 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -173,21 +173,21 @@ ADDR_E_RETURNCODE AddrLib1::ComputeSurfaceInfo(
}
}
// We suggest client do sanity check but a check here is also good
if (pIn->bpp > 128)
{
returnCode = ADDR_INVALIDPARAMS;
}
// Thick modes don't support multisample
- if (ComputeSurfaceThickness(pIn->tileMode) > 1 && pIn->numSamples > 1)
+ if (Thickness(pIn->tileMode) > 1 && pIn->numSamples > 1)
{
returnCode = ADDR_INVALIDPARAMS;
}
if (returnCode == ADDR_OK)
{
// Get a local copy of input structure and only reference pIn for unadjusted values
ADDR_COMPUTE_SURFACE_INFO_INPUT localIn = *pIn;
ADDR_TILEINFO tileInfoNull = {0};
@@ -817,21 +817,21 @@ ADDR_E_RETURNCODE AddrLib1::ComputeFmaskInfo(
if (GetFillSizeFieldsFlags() == TRUE)
{
if ((pIn->size != sizeof(ADDR_COMPUTE_FMASK_INFO_INPUT)) ||
(pOut->size != sizeof(ADDR_COMPUTE_FMASK_INFO_OUTPUT)))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
// No thick MSAA
- if (ComputeSurfaceThickness(pIn->tileMode) > 1)
+ if (Thickness(pIn->tileMode) > 1)
{
returnCode = ADDR_INVALIDPARAMS;
}
if (returnCode == ADDR_OK)
{
ADDR_TILEINFO tileInfoNull;
ADDR_COMPUTE_FMASK_INFO_INPUT input;
if (UseTileIndex(pIn->tileIndex))
@@ -1196,30 +1196,30 @@ ADDR_E_RETURNCODE AddrLib1::GetTileIndex(
if (returnCode == ADDR_OK)
{
returnCode = HwlGetTileIndex(pIn, pOut);
}
return returnCode;
}
/**
***************************************************************************************************
-* AddrLib1::ComputeSurfaceThickness
+* AddrLib1::Thickness
*
* @brief
* Compute surface thickness
*
* @return
* Surface thickness
***************************************************************************************************
*/
-UINT_32 AddrLib1::ComputeSurfaceThickness(
+UINT_32 AddrLib1::Thickness(
AddrTileMode tileMode) ///< [in] tile mode
{
return m_modeFlags[tileMode].thickness;
}
///////////////////////////////////////////////////////////////////////////////////////////////////
// CMASK/HTILE
///////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2769,21 +2769,21 @@ UINT_32 AddrLib1::ComputePixelIndexWithinMicroTile(
UINT_32 x0 = _BIT(x, 0);
UINT_32 x1 = _BIT(x, 1);
UINT_32 x2 = _BIT(x, 2);
UINT_32 y0 = _BIT(y, 0);
UINT_32 y1 = _BIT(y, 1);
UINT_32 y2 = _BIT(y, 2);
UINT_32 z0 = _BIT(z, 0);
UINT_32 z1 = _BIT(z, 1);
UINT_32 z2 = _BIT(z, 2);
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// Compute the pixel number within the micro tile.
if (microTileType != ADDR_THICK)
{
if (microTileType == ADDR_DISPLAYABLE)
{
switch (bpp)
{
case 8:
@@ -3000,21 +3000,21 @@ VOID AddrLib1::PadDimensions(
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
UINT_32* pPitch, ///< [in/out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pHeight, ///< [in/out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
UINT_32* pSlices, ///< [in/out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(padDims <= 3);
//
// Override padding for mip levels
//
if (mipLevel > 0)
{
if (flags.cube)
{
@@ -3286,21 +3286,21 @@ VOID AddrLib1::ComputeMipLevel(
* @return
* TRUE if degraded, also returns degraded tile mode (unchanged if not degraded)
***************************************************************************************************
*/
BOOL_32 AddrLib1::OptimizeTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure for surface info
AddrTileMode* pTileMode ///< [out] Degraded tile mode
) const
{
AddrTileMode tileMode = pIn->tileMode;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// Optimization can only be done on level 0 and samples <= 1
if ((pIn->flags.opt4Space == TRUE) &&
(pIn->mipLevel == 0) &&
(pIn->numSamples <= 1) &&
(pIn->flags.display == FALSE) &&
(IsPrtTileMode(tileMode) == FALSE) &&
(pIn->flags.prt == FALSE))
{
// Check if linear mode is optimal
@@ -3357,21 +3357,21 @@ BOOL_32 AddrLib1::OptimizeTileMode(
* The degraded tile mode (unchanged if not degraded)
***************************************************************************************************
*/
AddrTileMode AddrLib1::DegradeLargeThickTile(
AddrTileMode tileMode,
UINT_32 bpp) const
{
// Override tilemode
// When tile_width (8) * tile_height (8) * thickness * element_bytes is > row_size,
// it is better to just use THIN mode in this case
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
if (thickness > 1 && m_configFlags.allowLargeThickTile == 0)
{
UINT_32 tileSize = MicroTilePixels * thickness * (bpp >> 3);
if (tileSize > m_rowSize)
{
switch (tileMode)
{
case ADDR_TM_2D_TILED_XTHICK:
diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h
index 94ca5a5..13d915a 100644
--- a/src/amd/addrlib/core/addrlib1.h
+++ b/src/amd/addrlib/core/addrlib1.h
@@ -418,21 +418,21 @@ protected:
/// Pure Virtual function for Hwl computing coord Y for 8 pipe cmask/htile
virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, UINT_32 x) const = 0;
//
// Misc helper
//
static const AddrTileModeFlags m_modeFlags[ADDR_TM_COUNT];
- static UINT_32 ComputeSurfaceThickness(
+ static UINT_32 Thickness(
AddrTileMode tileMode);
// Checking tile mode
static BOOL_32 IsMacroTiled(AddrTileMode tileMode);
static BOOL_32 IsMacro3dTiled(AddrTileMode tileMode);
static BOOL_32 IsLinear(AddrTileMode tileMode);
static BOOL_32 IsMicroTiled(AddrTileMode tileMode);
static BOOL_32 IsPrtTileMode(AddrTileMode tileMode);
static BOOL_32 IsPrtNoRotationTileMode(AddrTileMode tileMode);
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index ccb0528..7585e25 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -629,21 +629,21 @@ ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg(
*pInfo = m_macroTileTable[macroModeIndex];
if (pCfgTable->type == ADDR_DEPTH_SAMPLE_ORDER)
{
tileSplit = pCfgTable->info.tileSplitBytes;
}
else
{
if (bpp > 0)
{
- UINT_32 thickness = ComputeSurfaceThickness(pCfgTable->mode);
+ UINT_32 thickness = Thickness(pCfgTable->mode);
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[index].info.tileSplitBytes;
tileSplit = Max(256u, sampleSplit * tileBytes1x);
}
else
{
// Return tileBytes instead if not enough info
tileSplit = pInfo->tileSplitBytes;
}
@@ -890,21 +890,21 @@ BOOL_32 CiAddrLib::HwlOverrideTileMode(
case ADDR_TM_PRT_3D_TILED_THIN1:
tileMode = ADDR_TM_PRT_TILED_THIN1;
break;
default:
break;
}
// UBTS#404321, we do not need such overriding, as THICK+THICK entries removed from the tile-mode table
if (!m_settings.isBonaire)
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// tile_thickness = (array_mode == XTHICK) ? 8 : ((array_mode == THICK) ? 4 : 1)
if (thickness > 1)
{
switch (pIn->format)
{
// see //gfxip/gcB/devel/cds/src/verif/tc/models/csim/tcp.cpp
// tcpError("Thick micro tiling is not supported for format...
case ADDR_FMT_X24_8_32_FLOAT:
case ADDR_FMT_32_AS_8:
@@ -993,21 +993,21 @@ VOID CiAddrLib::HwlSetupTileInfo(
UINT_32 bpp, ///< [in] Bits per pixel
UINT_32 pitch, ///< [in] Pitch in pixels
UINT_32 height, ///< [in] Height in pixels
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
AddrTileType inTileType, ///< [in] Tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_TILEINFO* pTileInfo = pTileInfoOut;
INT index = TileIndexInvalid;
INT macroModeIndex = TileIndexInvalid;
// Fail-safe code
if (!IsLinear(tileMode))
{
// Thick tile modes must use thick micro tile mode but Bonaire does not support due to
// old derived netlists (UBTS 404321)
if (thickness > 1)
@@ -1539,21 +1539,21 @@ INT_32 CiAddrLib::HwlComputeMacroModeIndex(
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfo, ///< [out] Pointer to ADDR_TILEINFO
AddrTileMode* pTileMode, ///< [out] Pointer to AddrTileMode
AddrTileType* pTileType ///< [out] Pointer to AddrTileType
) const
{
INT_32 macroModeIndex = TileIndexInvalid;
AddrTileMode tileMode = m_tileTable[tileIndex].mode;
AddrTileType tileType = m_tileTable[tileIndex].type;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
if (!IsMacroTiled(tileMode))
{
*pTileInfo = m_tileTable[tileIndex].info;
macroModeIndex = TileIndexNoMacroIndex;
}
else
{
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
UINT_32 tileSplit;
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 64c0c62..52cf59b 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -317,21 +317,21 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
UINT_32 expPitch = pIn->width;
UINT_32 expHeight = pIn->height;
UINT_32 expNumSlices = pIn->numSlices;
// No 1D MSAA on real H/W, keep this for TGL
UINT_32 numSamples = pOut->numSamples;
//
// Compute the micro tile thickness.
//
- microTileThickness = ComputeSurfaceThickness(expTileMode);
+ microTileThickness = Thickness(expTileMode);
//
// Extra override for mip levels
//
if (pIn->mipLevel > 0)
{
//
// Reduce tiling mode from thick to thin if the number of slices is less than the
// micro tile thickness.
//
@@ -448,21 +448,21 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
pOut->pTileInfo,
&pOut->baseAlign,
&pOut->pitchAlign,
&pOut->heightAlign);
if (valid)
{
//
// Compute the micro tile thickness.
//
- microTileThickness = ComputeSurfaceThickness(expTileMode);
+ microTileThickness = Thickness(expTileMode);
//
// Find the correct tiling mode for mip levels
//
if (pIn->mipLevel > 0)
{
//
// Try valid tile mode
//
expTileMode = ComputeSurfaceMipLevelTileMode(expTileMode,
@@ -474,21 +474,21 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
pOut->pitchAlign,
pOut->heightAlign,
pOut->pTileInfo);
if (!IsMacroTiled(expTileMode)) // Downgraded to micro-tiled
{
return ComputeSurfaceInfoMicroTiled(pIn, pOut, padDims, expTileMode);
}
else
{
- if (microTileThickness != ComputeSurfaceThickness(expTileMode))
+ if (microTileThickness != Thickness(expTileMode))
{
//
// Re-compute if thickness changed since bank-height may be changed!
//
return ComputeSurfaceInfoMacroTiled(pIn, pOut, padDims, expTileMode);
}
}
}
paddedPitch = expPitch;
@@ -804,21 +804,21 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMacroTiled(
if (valid)
{
UINT_32 macroTileWidth;
UINT_32 macroTileHeight;
UINT_32 tileSize;
UINT_32 bankHeightAlign;
UINT_32 macroAspectAlign;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
UINT_32 pipes = HwlGetPipes(pTileInfo);
//
// Align bank height first according to latest h/w spec
//
// tile_size = MIN(tile_split, 64 * tile_thickness * element_bytes * num_samples)
tileSize = Min(pTileInfo->tileSplitBytes,
BITS_TO_BYTES(64 * thickness * bpp * numSamples));
@@ -1020,21 +1020,21 @@ AddrTileMode EgBasedAddrLib::ComputeSurfaceMipLevelTileMode(
UINT_32 numSlices, ///< [in] current number of slices
UINT_32 numSamples, ///< [in] number of samples
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32 heightAlign, ///< [in] height alignment
ADDR_TILEINFO* pTileInfo ///< [in] ptr to bank structure
) const
{
UINT_32 bytesPerTile;
AddrTileMode expTileMode = baseTileMode;
- UINT_32 microTileThickness = ComputeSurfaceThickness(expTileMode);
+ UINT_32 microTileThickness = Thickness(expTileMode);
UINT_32 interleaveSize = m_pipeInterleaveBytes * m_bankInterleave;
//
// Compute the size of a slice.
//
bytesPerTile = BITS_TO_BYTES(MicroTilePixels * microTileThickness * NextPow2(bpp) * numSamples);
//
// Reduce tiling mode from thick to thin if the number of slices is less than the
// micro tile thickness.
@@ -1183,21 +1183,21 @@ BOOL_32 EgBasedAddrLib::HwlDegradeBaseLevel(
* @return
* Suitable tile mode
***************************************************************************************************
*/
AddrTileMode EgBasedAddrLib::HwlDegradeThickTileMode(
AddrTileMode baseTileMode, ///< [in] base tile mode
UINT_32 numSlices, ///< [in] current number of slices
UINT_32* pBytesPerTile ///< [in/out] pointer to bytes per slice
) const
{
- ADDR_ASSERT(numSlices < ComputeSurfaceThickness(baseTileMode));
+ ADDR_ASSERT(numSlices < Thickness(baseTileMode));
// if pBytesPerTile is NULL, this is a don't-care....
UINT_32 bytesPerTile = pBytesPerTile != NULL ? *pBytesPerTile : 64;
AddrTileMode expTileMode = baseTileMode;
switch (baseTileMode)
{
case ADDR_TM_1D_TILED_THICK:
expTileMode = ADDR_TM_1D_TILED_THIN1;
bytesPerTile >>= 2;
break;
@@ -1299,21 +1299,21 @@ UINT_64 EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord(
{
numSamples = numFrags;
ADDR_ASSERT(sample < numSamples);
}
/// @note
/// 128 bit/thick tiled surface doesn't support display tiling and
/// mipmap chain must have the same tileType, so please fill tileType correctly
if (IsLinear(pIn->tileMode) == FALSE)
{
- if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
+ if (bpp >= 128 || Thickness(tileMode) > 1)
{
ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
}
}
}
switch (tileMode)
{
case ADDR_TM_LINEAR_GENERAL://fall through
case ADDR_TM_LINEAR_ALIGNED:
@@ -1467,21 +1467,21 @@ UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMacroTiled(
UINT_64 pipeInterleaveMask;
UINT_64 bankInterleaveMask;
UINT_64 pipeInterleaveOffset;
UINT_32 bankInterleaveOffset;
UINT_64 offset;
UINT_32 tileRowIndex;
UINT_32 tileColumnIndex;
UINT_32 tileIndex;
UINT_32 tileOffset;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Compute the number of group, pipe, and bank bits.
//
UINT_32 numPipes = HwlGetPipes(pTileInfo);
UINT_32 numPipeInterleaveBits = Log2(m_pipeInterleaveBytes);
UINT_32 numPipeBits = Log2(numPipes);
UINT_32 numBankInterleaveBits = Log2(m_bankInterleave);
UINT_32 numBankBits = Log2(pTileInfo->banks);
@@ -1719,21 +1719,21 @@ UINT_64 EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled(
UINT_32 microTilesPerRow;
UINT_32 microTileIndexX;
UINT_32 microTileIndexY;
UINT_32 microTileIndexZ;
UINT_64 sliceOffset;
UINT_64 microTileOffset;
UINT_32 sampleOffset;
UINT_32 pixelIndex;
UINT_32 pixelOffset;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Compute the micro tile size.
//
microTileBytes = BITS_TO_BYTES(MicroTilePixels * microTileThickness * bpp * numSamples);
//
// Compute the slice size.
//
sliceBytes =
@@ -1832,21 +1832,21 @@ VOID EgBasedAddrLib::HwlComputePixelCoordFromOffset(
UINT_32* pY, ///< [out] y coordinate
UINT_32* pSlice, ///< [out] slice index
UINT_32* pSample, ///< [out] sample index
AddrTileType microTileType, ///< [in] micro tiling type
BOOL_32 isDepthSampleOrder ///< [in] TRUE if depth sample order in microtile is used
) const
{
UINT_32 x = 0;
UINT_32 y = 0;
UINT_32 z = 0;
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
// For planar surface, we adjust offset acoording to tile base
if ((bpp != compBits) && (compBits != 0) && isDepthSampleOrder)
{
offset -= tileBase;
ADDR_ASSERT(microTileType == ADDR_NON_DISPLAYABLE ||
microTileType == ADDR_DEPTH_SAMPLE_ORDER);
bpp = compBits;
@@ -2046,21 +2046,21 @@ VOID EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddr(
if (numFrags != numSamples)
{
numSamples = numFrags;
}
/// @note
/// 128 bit/thick tiled surface doesn't support display tiling and
/// mipmap chain must have the same tileType, so please fill tileType correctly
if (IsLinear(pIn->tileMode) == FALSE)
{
- if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
+ if (bpp >= 128 || Thickness(tileMode) > 1)
{
ADDR_ASSERT(microTileType != ADDR_DISPLAYABLE);
}
}
}
switch (tileMode)
{
case ADDR_TM_LINEAR_GENERAL://fall through
case ADDR_TM_LINEAR_ALIGNED:
@@ -2200,21 +2200,21 @@ VOID EgBasedAddrLib::ComputeSurfaceCoordFromAddrMacroTiled(
UINT_64 addrBits = BYTES_TO_BITS(addr) + bitPosition;
//
// remove bits for bank and pipe
//
totalOffset = (addrBits % groupBits) +
(((addrBits / groupBits / pipes) % bankInterleave) * groupBits) +
(((addrBits / groupBits / pipes) / bankInterleave) / banks) * groupBits * bankInterleave;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
UINT_32 microTileBits = bpp * microTileThickness * MicroTilePixels * numSamples;
UINT_32 microTileBytes = BITS_TO_BYTES(microTileBits);
//
// Determine if tiles need to be split across slices.
//
// If the size of the micro tile is larger than the tile split size, then the tile will be
// split across multiple slices.
//
@@ -2358,21 +2358,21 @@ VOID EgBasedAddrLib::ComputeSurfaceCoord2DFromBankPipe(
case ADDR_TM_3D_TILED_THIN1: //fall through
case ADDR_TM_3D_TILED_THICK: //fall through
case ADDR_TM_3D_TILED_XTHICK:
tileSplitRotation = ((pTileInfo->banks / 2) + 1);
break;
default:
tileSplitRotation = 0;
break;
}
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
bank ^= tileSplitRotation * tileSlices;
if (pipeRotation == 0)
{
bank ^= bankRotation * (slice / microTileThickness) + bankSwizzle;
bank %= pTileInfo->banks;
pipe ^= pipeSwizzle;
}
else
{
@@ -2696,21 +2696,21 @@ UINT_32 EgBasedAddrLib::ComputeSliceTileSwizzle(
UINT_32 baseSwizzle, ///< [in] Base swizzle
UINT_32 slice, ///< [in] Slice index, Cubemap face index, 0 means +X
UINT_64 baseAddr, ///< [in] Base address
ADDR_TILEINFO* pTileInfo ///< [in] Bank structure
) const
{
UINT_32 tileSwizzle = 0;
if (IsMacroTiled(tileMode)) // Swizzle only for macro tile mode
{
- UINT_32 firstSlice = slice / ComputeSurfaceThickness(tileMode);
+ UINT_32 firstSlice = slice / Thickness(tileMode);
UINT_32 numPipes = HwlGetPipes(pTileInfo);
UINT_32 numBanks = pTileInfo->banks;
UINT_32 pipeRotation;
UINT_32 bankRotation;
UINT_32 bankSwizzle = 0;
UINT_32 pipeSwizzle = 0;
@@ -2852,21 +2852,21 @@ UINT_32 EgBasedAddrLib::ComputeBankFromCoord(
}
bank = bankBit0 | (bankBit1 << 1) | (bankBit2 << 2) | (bankBit3 << 3);
//Bits2Number(4, bankBit3, bankBit2, bankBit1, bankBit0);
bank = HwlPreAdjustBank((x / MicroTileWidth), bank, pTileInfo);
//
// Compute bank rotation for the slice.
//
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
switch (tileMode)
{
case ADDR_TM_2D_TILED_THIN1: // fall through
case ADDR_TM_2D_TILED_THICK: // fall through
case ADDR_TM_2D_TILED_XTHICK:
sliceRotation = ((numBanks / 2) - 1) * (slice / microTileThickness);
break;
case ADDR_TM_3D_TILED_THIN1: // fall through
case ADDR_TM_3D_TILED_THICK: // fall through
@@ -3274,21 +3274,21 @@ UINT_64 EgBasedAddrLib::DispatchComputeFmaskAddrFromCoord(
UINT_32 numSamples = pIn->numSamples;
AddrTileMode tileMode = pIn->tileMode;
BOOL_32 ignoreSE = pIn->ignoreSE;
ADDR_TILEINFO* pTileInfo = pIn->pTileInfo;
BOOL_32 resolved = pIn->resolved;
UINT_32* pBitPosition = &pOut->bitPosition;
UINT_64 addr = 0;
ADDR_ASSERT(numSamples > 1);
- ADDR_ASSERT(ComputeSurfaceThickness(tileMode) == 1);
+ ADDR_ASSERT(Thickness(tileMode) == 1);
switch (tileMode)
{
case ADDR_TM_1D_TILED_THIN1:
addr = ComputeFmaskAddrFromCoordMicroTiled(x,
y,
slice,
sample,
plane,
pitch,
@@ -4505,21 +4505,21 @@ UINT_32 EgBasedAddrLib::HwlComputeHtileBaseAlign(
*/
UINT_32 EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples ///< [in] number of samples
) const
{
UINT_32 pitchAlign;
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
UINT_32 pixelsPerMicroTile;
UINT_32 pixelsPerPipeInterleave;
UINT_32 microTilesPerPipeInterleave;
//
// Special workaround for depth/stencil buffer, use 8 bpp to meet larger requirement for
// stencil buffer since pitch alignment is related to bpp.
// For a depth only buffer do not set this.
//
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 5d725e6..694c0f3 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -285,21 +285,21 @@ UINT_32 SiAddrLib::ComputePipeFromCoord(
pipeBit2 = x5 ^ y6;
pipeBit3 = x6 ^ y5;
numPipes = 16;
break;
default:
ADDR_UNHANDLED_CASE();
break;
}
pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
- UINT_32 microTileThickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 microTileThickness = Thickness(tileMode);
//
// Apply pipe rotation for the slice.
//
switch (tileMode)
{
case ADDR_TM_3D_TILED_THIN1: //fall through thin
case ADDR_TM_3D_TILED_THICK: //fall through thick
case ADDR_TM_3D_TILED_XTHICK:
sliceRotation =
@@ -1453,21 +1453,21 @@ VOID SiAddrLib::HwlSetupTileInfo(
UINT_32 bpp, ///< [in] Bits per pixel
UINT_32 pitch, ///< [in] Pitch in pixels
UINT_32 height, ///< [in] Height in pixels
UINT_32 numSamples, ///< [in] Number of samples
ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
AddrTileType inTileType, ///< [in] Tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
) const
{
- UINT_32 thickness = ComputeSurfaceThickness(tileMode);
+ UINT_32 thickness = Thickness(tileMode);
ADDR_TILEINFO* pTileInfo = pTileInfoOut;
INT index = TileIndexInvalid;
// Fail-safe code
if (IsLinear(tileMode) == FALSE)
{
// 128 bpp/thick tiling must be non-displayable.
// Fmask reuse color buffer's entry but bank-height field can be from another entry
// To simplify the logic, fmask entry should be picked from non-displayable ones
if (bpp == 128 || thickness > 1 || flags.fmask || flags.prt)
--
2.7.4
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