[Mesa-dev] [PATCH 036/140] amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:42:46 UTC 2017
From: Nicolai Hähnle <nicolai.haehnle at amd.com>
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
---
src/amd/addrlib/core/addrlib1.cpp | 12 +++----
src/amd/addrlib/core/addrlib1.h | 10 +++---
src/amd/addrlib/r800/ciaddrlib.cpp | 66 ++++++++++++++++++++++++++++---------
src/amd/addrlib/r800/ciaddrlib.h | 11 +++++--
src/amd/addrlib/r800/egbaddrlib.cpp | 25 ++++----------
src/amd/addrlib/r800/egbaddrlib.h | 8 +++++
src/amd/addrlib/r800/siaddrlib.cpp | 42 +++++++++++++++++++++++
src/amd/addrlib/r800/siaddrlib.h | 6 ++++
8 files changed, 131 insertions(+), 49 deletions(-)
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index d48aa7c..040891c 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -3221,27 +3221,28 @@ VOID Lib::AdjustPitchAlignment(
*/
VOID Lib::PadDimensions(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
UINT_32* pPitch, ///< [in,out] pitch in pixels
- UINT_32 pitchAlign, ///< [in] pitch alignment
+ UINT_32* pPitchAlign, ///< [in,out] pitch align could be changed in HwlPadDimensions
UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
+ UINT_32 pitchAlign = *pPitchAlign;
UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(padDims <= 3);
//
// Override padding for mip levels
//
if (mipLevel > 0)
{
if (flags.cube)
@@ -3295,28 +3296,25 @@ VOID Lib::PadDimensions(
*pSlices = PowTwoAlign((*pSlices), sliceAlign);
}
}
HwlPadDimensions(tileMode,
bpp,
flags,
numSamples,
pTileInfo,
- padDims,
mipLevel,
pPitch,
- pitchAlign,
- pHeight,
- heightAlign,
- pSlices,
- sliceAlign);
+ pPitchAlign,
+ *pHeight,
+ heightAlign);
}
/**
****************************************************************************************************
* Lib::HwlPreHandleBaseLvl3xPitch
*
* @brief
* Pre-handler of 3x pitch (96 bit) adjustment
*
diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h
index 9c66f53..c1fc693 100644
--- a/src/amd/addrlib/core/addrlib1.h
+++ b/src/amd/addrlib/core/addrlib1.h
@@ -64,20 +64,23 @@ struct TileModeFlags
UINT_32 thickness : 4;
UINT_32 isLinear : 1;
UINT_32 isMicro : 1;
UINT_32 isMacro : 1;
UINT_32 isMacro3d : 1;
UINT_32 isPrt : 1;
UINT_32 isPrtNoRotation : 1;
UINT_32 isBankSwapped : 1;
};
+static const UINT_32 Block64K = 0x10000;
+static const UINT_32 PrtTileSize = Block64K;
+
/**
****************************************************************************************************
* @brief This class contains asic independent address lib functionalities
****************************************************************************************************
*/
class Lib : public Addr::Lib
{
public:
virtual ~Lib();
@@ -358,28 +361,27 @@ protected:
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
AddrTileMode DegradeLargeThickTile(AddrTileMode tileMode, UINT_32 bpp) const;
VOID PadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
- UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
+ UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
- UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
- UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
- UINT_32* pSlices, UINT_32 sliceAlign) const
+ UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
+ UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32 height, UINT_32 heightAlign) const
{
}
//
// Addressing shared for linear/1D tiling
//
UINT_64 ComputeSurfaceAddrFromCoordLinear(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32* pBitPosition) const;
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 3986c3b..3509024 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1934,98 +1934,132 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
///--------------------------------------------------------------------------------------------
lsb = pipeInterleaveBits + 1; ///<+1 due to Nibble address now gives interleave bits extra lsb.
msb = pipeBits - 1 + lsb;
UINT_64 metadataAddress = InsertBits(metaAddressInPipe, pipeDataBits, msb, lsb);
return metadataAddress;
}
/**
****************************************************************************************************
+* CiLib::HwlComputeSurfaceAlignmentsMacroTiled
+*
+* @brief
+* Hardware layer function to compute alignment request for macro tile mode
+*
+* @return
+* N/A
+*
+****************************************************************************************************
+*/
+VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, ///< [in] tile mode
+ UINT_32 bpp, ///< [in] bits per pixel
+ ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
+ UINT_32 mipLevel, ///< [in] mip level
+ UINT_32 numSamples, ///< [in] number of samples
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
+ UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
+ UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
+ UINT_32* pHeightAlign, ///< [out] height alignment in pixels
+ UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels
+ UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels
+ ) const
+{
+ if ((m_settings.isFiji == TRUE) &&
+ (flags.dccCompatible == TRUE) &&
+ (mipLevel == 0) &&
+ (tileMode == ADDR_TM_PRT_TILED_THIN1))
+ {
+ *pPitchAlign = PowTwoAlign(*pPitchAlign, 256);
+ }
+}
+
+/**
+****************************************************************************************************
* CiLib::HwlPadDimensions
*
* @brief
* Helper function to pad dimensions
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlPadDimensions(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
- UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
- UINT_32 mipLevel, ///< [in] MipLevel
+ ADDR_TILEINFO* pTileInfo, ///< [in] tile info
+ UINT_32 mipLevel, ///< [in] mip level
UINT_32* pPitch, ///< [in,out] pitch in pixels
- UINT_32 pitchAlign, ///< [in] pitch alignment
- UINT_32* pHeight, ///< [in,out] height in pixels
- UINT_32 heightAlign, ///< [in] height alignment
- UINT_32* pSlices, ///< [in,out] number of slices
- UINT_32 sliceAlign ///< [in] number of slice alignment
+ UINT_32* pPitchAlign, ///< [in,out] pitch alignment
+ UINT_32 height, ///< [in] height in pixels
+ UINT_32 heightAlign ///< [in] height alignment
) const
{
- if (m_settings.isVolcanicIslands &&
- flags.dccCompatible &&
+ if ((m_settings.isVolcanicIslands == TRUE) &&
+ (flags.dccCompatible == TRUE) &&
(numSamples > 1) &&
(mipLevel == 0) &&
- IsMacroTiled(tileMode))
+ (IsMacroTiled(tileMode) == TRUE))
{
UINT_32 tileSizePerSample = BITS_TO_BYTES(bpp * MicroTileWidth * MicroTileHeight);
UINT_32 samplesPerSplit = pTileInfo->tileSplitBytes / tileSizePerSample;
if (samplesPerSplit < numSamples)
{
UINT_32 dccFastClearByteAlign = HwlGetPipes(pTileInfo) * m_pipeInterleaveBytes * 256;
- UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * (*pHeight) * bpp * samplesPerSplit);
+ UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * height * bpp * samplesPerSplit);
ADDR_ASSERT(IsPow2(dccFastClearByteAlign));
if (0 != (bytesPerSplit & (dccFastClearByteAlign - 1)))
{
UINT_32 dccFastClearPixelAlign = dccFastClearByteAlign /
BITS_TO_BYTES(bpp) /
samplesPerSplit;
- UINT_32 macroTilePixelAlign = pitchAlign * heightAlign;
+ UINT_32 macroTilePixelAlign = (*pPitchAlign) * heightAlign;
if ((dccFastClearPixelAlign >= macroTilePixelAlign) &&
((dccFastClearPixelAlign % macroTilePixelAlign) == 0))
{
UINT_32 dccFastClearPitchAlignInMacroTile =
dccFastClearPixelAlign / macroTilePixelAlign;
- UINT_32 heightInMacroTile = *pHeight / heightAlign;
- UINT_32 dccFastClearPitchAlignInPixels;
+ UINT_32 heightInMacroTile = height / heightAlign;
while ((heightInMacroTile > 1) &&
((heightInMacroTile % 2) == 0) &&
(dccFastClearPitchAlignInMacroTile > 1) &&
((dccFastClearPitchAlignInMacroTile % 2) == 0))
{
heightInMacroTile >>= 1;
dccFastClearPitchAlignInMacroTile >>= 1;
}
- dccFastClearPitchAlignInPixels = pitchAlign * dccFastClearPitchAlignInMacroTile;
+ UINT_32 dccFastClearPitchAlignInPixels =
+ (*pPitchAlign) * dccFastClearPitchAlignInMacroTile;
if (IsPow2(dccFastClearPitchAlignInPixels))
{
*pPitch = PowTwoAlign((*pPitch), dccFastClearPitchAlignInPixels);
}
else
{
*pPitch += (dccFastClearPitchAlignInPixels - 1);
*pPitch /= dccFastClearPitchAlignInPixels;
*pPitch *= dccFastClearPitchAlignInPixels;
}
+
+ *pPitchAlign = dccFastClearPitchAlignInPixels;
}
}
}
}
}
/**
****************************************************************************************************
* CiLib::HwlGetMaxAlignments
*
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index a9b1607..c59a0b1 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -159,23 +159,28 @@ protected:
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
- UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
- UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
- UINT_32* pSlices, UINT_32 sliceAlign) const;
+ UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
+ UINT_32* pPitch, UINT_32 *PitchAlign, UINT_32 height, UINT_32 heightAlign) const;
+
+ virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
+ UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
+ UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
+ UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, TileConfig* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index b151682..9655c47 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -257,21 +257,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoLinear(
//
// Pad pitch and height to the required granularities.
//
PadDimensions(pIn->tileMode,
pIn->bpp,
pIn->flags,
numSamples,
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &expPitch, pOut->pitchAlign,
+ &expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
expPitch = HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
//
// Adjust per HWL
//
UINT_64 logicalSliceSize;
@@ -371,21 +371,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
// Compute surface size.
// Return parameters.
//
PadDimensions(expTileMode,
pIn->bpp,
pIn->flags,
numSamples,
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &expPitch, pOut->pitchAlign,
+ &expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
//
// Get HWL specific pitch adjustment
//
UINT_64 logicalSliceSize = HwlGetSizeAdjustmentMicroTiled(microTileThickness,
pIn->bpp,
pIn->flags,
numSamples,
@@ -520,21 +520,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
//
// Do padding
//
PadDimensions(expTileMode,
pIn->bpp,
pIn->flags,
numSamples,
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &paddedPitch, pOut->pitchAlign,
+ &paddedPitch, &pOut->pitchAlign,
&paddedHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
if (pIn->flags.qbStereo &&
(pOut->pStereoInfo != NULL))
{
UINT_32 stereoHeightAlign = HwlStereoCheckRightOffsetPadding(pOut->pTileInfo);
if (stereoHeightAlign != 0)
{
@@ -925,36 +925,23 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
*pHeightAlign = macroTileHeight;
*pMacroTileHeight = macroTileHeight;
//
// Compute base alignment
//
*pBaseAlign = pipes *
pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
- if ((mipLevel == 0) && (flags.prt) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
- {
- static const UINT_32 PrtTileSize = 0x10000;
-
- UINT_32 macroTileSize = macroTileWidth * macroTileHeight * numSamples * bpp / 8;
-
- if (macroTileSize < PrtTileSize)
- {
- UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
-
- ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
-
- *pPitchAlign *= numMacroTiles;
- *pBaseAlign *= numMacroTiles;
- }
- }
+ HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples,
+ pTileInfo, pBaseAlign, pPitchAlign, pHeightAlign,
+ pMacroTileWidth, pMacroTileHeight);
}
return valid;
}
/**
****************************************************************************************************
* EgBasedLib::SanityCheckMacroTiled
*
* @brief
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index c397cfc..1a56003 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -293,20 +293,28 @@ protected:
ADDR_E_RETURNCODE ComputeMacroTileEquation(
UINT_32 log2BytesPP, AddrTileMode tileMode, AddrTileType microTileType,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
// Static functions
static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
+ virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
+ UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
+ UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
+ UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const
+ {
+ }
+
private:
BOOL_32 ComputeSurfaceInfoLinear(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims) const;
BOOL_32 ComputeSurfaceInfoMicroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 512fb27..f8f9379 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -3320,20 +3320,62 @@ ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments(
if (pOut != NULL)
{
pOut->baseAlign = maxBaseAlign;
}
return ADDR_OK;
}
/**
****************************************************************************************************
+* SiLib::HwlComputeSurfaceAlignmentsMacroTiled
+*
+* @brief
+* Hardware layer function to compute alignment request for macro tile mode
+*
+* @return
+* N/A
+*
+****************************************************************************************************
+*/
+VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, ///< [in] tile mode
+ UINT_32 bpp, ///< [in] bits per pixel
+ ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
+ UINT_32 mipLevel, ///< [in] mip level
+ UINT_32 numSamples, ///< [in] number of samples
+ ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
+ UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
+ UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
+ UINT_32* pHeightAlign, ///< [out] height alignment in pixels
+ UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels
+ UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels
+ ) const
+{
+ if ((mipLevel == 0) && (flags.prt))
+ {
+ UINT_32 macroTileSize = (*pMacroTileWidth) * (*pMacroTileHeight) * numSamples * bpp / 8;
+
+ if (macroTileSize < PrtTileSize)
+ {
+ UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
+
+ ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
+
+ *pPitchAlign *= numMacroTiles;
+ *pBaseAlign *= numMacroTiles;
+ }
+ }
+}
+
+/**
+****************************************************************************************************
* SiLib::InitEquationTable
*
* @brief
* Initialize Equation table.
*
* @return
* N/A
****************************************************************************************************
*/
VOID SiLib::InitEquationTable()
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index b63d7e8..c40b546 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -234,20 +234,26 @@ protected:
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
+ virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
+ UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
+ UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
+ UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+
// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
// Check if it is supported for given bpp and tile config to generate an equation
BOOL_32 IsEquationSupported(
--
2.7.4
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