[Mesa-dev] [PATCH 050/140] amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags

[Marek Olšák]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
---
 src/amd/addrlib/addrinterface.h    | 6 +++++-
 src/amd/addrlib/core/addrlib1.cpp  | 2 ++
 src/amd/addrlib/r800/ciaddrlib.cpp | 4 ++--
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index d2d6d94..14dff66 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -497,21 +497,25 @@ typedef union _ADDR_SURFACE_FLAGS
         UINT_32 noStencil            : 1; ///< Flag indicates this depth has no separate stencil
         UINT_32 display              : 1; ///< Flag indicates this should match display controller req.
         UINT_32 opt4Space            : 1; ///< Flag indicates this surface should be optimized for space
                                           ///  i.e. save some memory but may lose performance
         UINT_32 prt                  : 1; ///< Flag for partially resident texture
         UINT_32 qbStereo             : 1; ///< Quad buffer stereo surface
         UINT_32 pow2Pad              : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
         UINT_32 interleaved          : 1; ///< Special flag for interleaved YUV surface padding
         UINT_32 tcCompatible         : 1; ///< Flag indicates surface needs to be shader readable
         UINT_32 dispTileType         : 1; ///< NI: force display Tiling for 128 bit shared resoruce
-        UINT_32 dccCompatible        : 1; ///< VI: whether to support dcc fast clear
+        UINT_32 dccCompatible        : 1; ///< VI: whether to make MSAA surface support dcc fast clear
+        UINT_32 dccPipeWorkaround    : 1; ///< VI: whether to workaround the HW limit that
+                                          ///  dcc can't be enabled if pipe config of tile mode
+                                          ///  is different from that of ASIC, this flag
+                                          ///  is address lib internal flag, client should ignore it
         UINT_32 czDispCompatible     : 1; ///< SI+: CZ family has a HW bug needs special alignment.
                                           ///  This flag indicates we need to follow the
                                           ///  alignment with CZ families or other ASICs under
                                           ///  PX configuration + CZ.
         UINT_32 nonSplit             : 1; ///< CI: depth texture should not be split
         UINT_32 disableLinearOpt     : 1; ///< Disable tile mode optimization to linear
         UINT_32 needEquation         : 1; ///< Make the surface tile setting equation compatible.
                                           ///  This flag indicates we need to override tile
                                           ///  mode to PRT_* tile mode to disable slice rotation,
                                           ///  which is needed by swizzle pattern equation.
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index 809bca2..2d640cf 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -329,20 +329,22 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
                 {
                     ADDR_ASSERT(!IsMacroTiled(localIn.tileMode));
                 }
 
                 pOut->macroModeIndex = macroModeIndex;
             }
         }
 
         if (returnCode == ADDR_OK)
         {
+            localIn.flags.dccPipeWorkaround = localIn.flags.dccCompatible;
+
             if (localIn.tileMode == ADDR_TM_UNKNOWN)
             {
                 // HWL layer may override tile mode if necessary
                 HwlSelectTileMode(&localIn);
             }
             else
             {
                 // HWL layer may override tile mode if necessary
                 HwlOverrideTileMode(&localIn);
 
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 5ccc5da..1f7bb18 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -972,21 +972,21 @@ VOID CiLib::HwlOptimizeTileMode(
                     else
                     {
                         tileMode = ADDR_TM_PRT_TILED_THIN1;
                     }
                 }
             }
         }
 
         if (pInOut->maxBaseAlign != 0)
         {
-            pInOut->flags.dccCompatible = FALSE;
+            pInOut->flags.dccPipeWorkaround = FALSE;
         }
     }
 
     if (tileMode != pInOut->tileMode)
     {
         pInOut->tileMode = tileMode;
     }
 }
 
 /**
@@ -2088,21 +2088,21 @@ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
     ADDR_SURFACE_FLAGS                flags,              ///< [in] surface flags
     UINT_32                           mipLevel,           ///< [in] mip level
     UINT_32                           numSamples,         ///< [in] number of samples
     ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut                ///< [in,out] Surface output
     ) const
 {
     // This is to workaround a H/W limitation that DCC doesn't work when pipe config is switched to
     // P4. In theory, all asics that have such switching should be patched but we now only know what
     // to pad for Fiji.
     if ((m_settings.isFiji == TRUE) &&
-        (flags.dccCompatible == TRUE) &&
+        (flags.dccPipeWorkaround == TRUE) &&
         (flags.prt == FALSE) &&
         (mipLevel == 0) &&
         (tileMode == ADDR_TM_PRT_TILED_THIN1) &&
         (pOut->dccUnsupport == TRUE))
     {
         pOut->pitchAlign   = PowTwoAlign(pOut->pitchAlign, 256);
         // In case the client still requests DCC usage.
         pOut->dccUnsupport = FALSE;
     }
 }
-- 
2.7.4