[Mesa-dev] [PATCH 086/140] radeonsi/gfx9: add a scissor bug workaround

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_draw.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 1ff1547..8c6e9cd 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1162,20 +1162,26 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
 	si_need_cs_space(sctx);
 
 	/* Since we've called r600_context_add_resource_size for vertex buffers,
 	 * this must be called after si_need_cs_space, because we must let
 	 * need_cs_space flush before we add buffers to the buffer list.
 	 */
 	if (!si_upload_vertex_buffer_descriptors(sctx))
 		return;
 
+	/* GFX9 scissor bug workaround. There is also a more efficient but
+	 * more involved alternative workaround. */
+	if (sctx->b.chip_class == GFX9 &&
+	    si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
+		sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+
 	/* Flush caches before the first state atom, which does L2 prefetches. */
 	if (sctx->b.flags)
 		si_emit_cache_flush(sctx);
 
 	/* Emit state atoms. */
 	mask = sctx->dirty_atoms;
 	while (mask) {
 		struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
 
 		atom->emit(&sctx->b, atom);
-- 
2.7.4