[Mesa-dev] [PATCH 095/140] winsys/amdgpu: update amdgpu_addr_create for GFX9

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 47 ++++++++++++++++----------
 1 file changed, 30 insertions(+), 17 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index ede8ba6..c64865f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -36,6 +36,9 @@
 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
 #endif
 
+#ifndef CIASICIDGFXENGINE_ARCTICISLAND
+#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
+#endif
 
 static int amdgpu_surface_sanity(const struct pipe_resource *tex)
 {
@@ -107,32 +110,42 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 
-   regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
-   regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
-
-   regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
-   regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
-   regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
-   if (ws->info.chip_class == SI) {
-      regValue.pMacroTileConfig = NULL;
-      regValue.noOfMacroEntries = 0;
+   createFlags.value = 0;
+
+   if (ws->info.chip_class >= GFX9) {
+      addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
+      regValue.blockVarSizeLog2 = 0;
    } else {
-      regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
-      regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
-   }
+      regValue.backendDisables = ws->amdinfo.backend_disable[0];
+      regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
+      regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 
-   createFlags.value = 0;
-   createFlags.useTileIndex = 1;
-   createFlags.useHtileSliceAlign = 1;
+      regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
+      regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
+      regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
+      if (ws->info.chip_class == SI) {
+         regValue.pMacroTileConfig = NULL;
+         regValue.noOfMacroEntries = 0;
+      } else {
+         regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
+         regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
+      }
+
+      createFlags.useTileIndex = 1;
+      createFlags.useHtileSliceAlign = 1;
+
+      addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
+      addrCreateInput.chipFamily = ws->family;
+      addrCreateInput.chipRevision = ws->rev_id;
+   }
 
-   addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
    addrCreateInput.chipFamily = ws->family;
    addrCreateInput.chipRevision = ws->rev_id;
-   addrCreateInput.createFlags = createFlags;
    addrCreateInput.callbacks.allocSysMem = allocSysMem;
    addrCreateInput.callbacks.freeSysMem = freeSysMem;
    addrCreateInput.callbacks.debugPrint = 0;
+   addrCreateInput.createFlags = createFlags;
    addrCreateInput.regValue = regValue;
 
    addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
-- 
2.7.4