[Mesa-dev] [PATCH 3/8] genxml: Rename two MCS fields to Auxiliary Surface on gen7
Jason Ekstrand
jason at jlekstrand.net
Fri Mar 24 21:35:19 UTC 2017
This makes gen7 more consistent with gen8+
---
src/intel/genxml/gen7.xml | 4 ++--
src/intel/genxml/gen75.xml | 4 ++--
src/intel/isl/isl_surface_state.c | 7 +++----
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 3f3b188..40927ef 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -672,8 +672,8 @@
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Append Counter Address" start="198" end="223" type="address"/>
<field name="Append Counter Enable" start="193" end="193" type="bool"/>
- <field name="MCS Base Address" start="204" end="223" type="address"/>
- <field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
+ <field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
+ <field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
<field name="MCS Enable" start="192" end="192" type="bool"/>
<field name="Reserved: MBZ" start="222" end="223" type="uint"/>
<field name="X Offset for UV Plane" start="208" end="221" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 91fe02f..7b5c2af 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -683,8 +683,8 @@
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Append Counter Address" start="198" end="223" type="address"/>
<field name="Append Counter Enable" start="193" end="193" type="bool"/>
- <field name="MCS Base Address" start="204" end="223" type="address"/>
- <field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
+ <field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
+ <field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
<field name="MCS Enable" start="192" end="192" type="bool"/>
<field name="Reserved: MBZ" start="222" end="223" type="uint"/>
<field name="X Offset for UV Plane" start="208" end="221" type="uint"/>
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 853bb11..fa46469 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -548,16 +548,17 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
uint32_t pitch_in_tiles =
info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
+ s.AuxiliarySurfaceBaseAddress = info->aux_address;
+ s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
+
#if GEN_GEN >= 8
assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
- s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
/* Auxiliary surfaces in ISL have compressed formats but the hardware
* doesn't expect our definition of the compression, it expects qpitch
* in units of samples on the main surface.
*/
s.AuxiliarySurfaceQPitch =
isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
- s.AuxiliarySurfaceBaseAddress = info->aux_address;
if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
/* The number of samples must be 1 */
@@ -582,8 +583,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#else
assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
info->aux_usage == ISL_AUX_USAGE_CCS_D);
- s.MCSBaseAddress = info->aux_address,
- s.MCSSurfacePitch = pitch_in_tiles - 1;
s.MCSEnable = true;
#endif
}
--
2.5.0.400.gff86faf
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