[Mesa-dev] [PATCH 3/4] radv: fix ia_multi_vgt_param for instanced vs indirect draw.
Dave Airlie
airlied at gmail.com
Mon Mar 27 20:14:32 UTC 2017
From: Dave Airlie <airlied at redhat.com>
The logic was different than radeonsi, fix it up before adding
tess support.
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 13 +++++++------
src/amd/vulkan/radv_private.h | 3 ++-
src/amd/vulkan/si_cmd_buffer.c | 12 ++++++------
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 527184f..475f645 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1346,7 +1346,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
}
static void
-radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool instanced_or_indirect_draw,
+radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
+ bool instanced_draw, bool indirect_draw,
uint32_t draw_vertex_count)
{
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
@@ -1411,7 +1412,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool instanced_o
if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
radv_emit_scissor(cmd_buffer);
- ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_or_indirect_draw, draw_vertex_count);
+ ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
@@ -2325,7 +2326,7 @@ void radv_CmdDraw(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), vertexCount);
+ radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
@@ -2376,7 +2377,7 @@ void radv_CmdDrawIndexed(
uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
uint64_t index_va;
- radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), indexCount);
+ radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
radv_emit_primitive_reset_index(cmd_buffer);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
@@ -2474,7 +2475,7 @@ radv_cmd_draw_indirect_count(VkCommandBuffer command
uint32_t stride)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- radv_cmd_buffer_flush_state(cmd_buffer, true, 0);
+ radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
cmd_buffer->cs, 14);
@@ -2499,7 +2500,7 @@ radv_cmd_draw_indexed_indirect_count(
int index_size = cmd_buffer->state.index_type ? 4 : 2;
uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
uint64_t index_va;
- radv_cmd_buffer_flush_state(cmd_buffer, true, 0);
+ radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
radv_emit_primitive_reset_index(cmd_buffer);
index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e4654bb..433cba7 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -759,7 +759,8 @@ void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
void si_write_scissors(struct radeon_winsys_cs *cs, int first,
int count, const VkRect2D *scissors);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
- bool instanced_or_indirect_draw, uint32_t draw_vertex_count);
+ bool instanced_draw, bool indirect_draw,
+ uint32_t draw_vertex_count);
void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
enum chip_class chip_class,
bool is_mec,
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index acdd0de..82a2ea8 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -582,7 +582,7 @@ radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
uint32_t
si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
- bool instanced_or_indirect_draw,
+ bool instanced_draw, bool indirect_draw,
uint32_t draw_vertex_count)
{
enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
@@ -603,8 +603,8 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
primgroup_size = 64; /* recommended with a GS */
- multi_instances_smaller_than_primgroup = (instanced_or_indirect_draw ||
- num_prims < primgroup_size);
+ multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
+ num_prims < primgroup_size);
/* TODO TES */
/* TODO linestipple */
@@ -629,7 +629,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
* We don't know that for indirect drawing, so treat it as
* always problematic. */
if (family == CHIP_HAWAII &&
- instanced_or_indirect_draw)
+ (instanced_draw || indirect_draw))
wd_switch_on_eop = true;
/* Performance recommendation for 4 SE Gfx7-8 parts if
@@ -655,7 +655,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
/* Instancing bug on Bonaire. */
if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
- instanced_or_indirect_draw)
+ (instanced_draw || indirect_draw))
partial_vs_wave = true;
/* If the WD switch is false, the IA switch must be false too. */
@@ -673,7 +673,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
/* Hw bug with single-primitive instances and SWITCH_ON_EOI
* on multi-SE chips. */
if (info->max_se >= 2 && ia_switch_on_eoi &&
- (instanced_or_indirect_draw &&
+ ((instanced_draw || indirect_draw) &&
num_prims <= 1))
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
}
--
2.9.3
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