[Mesa-dev] [PATCH v3] i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+

[Alejandro Piñeiro]

Technically those hw operations are only available on gen7, as gen8+
support the conversion on the MOV. But, when using the builder to
implement nir operations (example: nir_op_fquantize2f16), it is not
needed to do the gen check. This check is done later, on the final
emission at brw_F32TO16 (brw_eu_emit), choosing between the MOV or the
specific operation accordingly.

So in the middle, during optimization phases those hw operations can
be around for gen8+ too.

Without this patch, several (at least 95) vulkan-cts quantize tests
crashes when using INTEL_DEBUG=optimizer. For example:
dEQP-VK.spirv_assembly.instruction.graphics.opquantize.too_small_vert

v2: simplify the code using GEN_GE (Ilia Mirkin)
v3: tweak brw_instruction_name instead of changing opcode_descs
    table, that is used for validation (Matt Turner)
---

Im not really proud of the comment, but I hope it explains well
why it is needed. Comments are welcome.

 src/intel/compiler/brw_shader.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index bfaa5e7..73bbc93 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -157,6 +157,15 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
          return "do";
 
+      /* The following conversion opcodes doesn't exist on Gen8+, but we use
+       * then to mark that we want to do the conversion.
+       */
+      if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
+         return "f32to16";
+
+      if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
+         return "f16to32";
+
       assert(brw_opcode_desc(devinfo, op)->name);
       return brw_opcode_desc(devinfo, op)->name;
    case FS_OPCODE_FB_WRITE:
-- 
2.9.3