[Mesa-dev] [PATCH] gallium: remove support for predicates from TGSI
Marek Olšák
maraeo at gmail.com
Wed Mar 29 15:51:02 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
Neved used.
---
src/gallium/auxiliary/gallivm/lp_bld_limits.h | 4 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h | 2 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c | 46 -------
src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c | 6 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 137 ++-----------------
src/gallium/auxiliary/tgsi/tgsi_build.c | 66 ---------
src/gallium/auxiliary/tgsi/tgsi_build.h | 3 -
src/gallium/auxiliary/tgsi/tgsi_dump.c | 24 ----
src/gallium/auxiliary/tgsi/tgsi_exec.c | 59 --------
src/gallium/auxiliary/tgsi/tgsi_exec.h | 7 -
src/gallium/auxiliary/tgsi/tgsi_parse.c | 4 -
src/gallium/auxiliary/tgsi/tgsi_parse.h | 1 -
src/gallium/auxiliary/tgsi/tgsi_sanity.c | 1 -
src/gallium/auxiliary/tgsi/tgsi_strings.c | 1 -
src/gallium/auxiliary/tgsi/tgsi_text.c | 37 -----
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 84 +-----------
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 149 +--------------------
src/gallium/docs/source/screen.rst | 1 -
src/gallium/drivers/freedreno/freedreno_screen.c | 2 -
src/gallium/drivers/i915/i915_fpc.h | 1 -
src/gallium/drivers/i915/i915_screen.c | 2 -
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 10 +-
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 -
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 -
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 -
src/gallium/drivers/r300/r300_screen.c | 4 -
src/gallium/drivers/r600/r600_pipe.c | 2 -
src/gallium/drivers/r600/r600_shader.c | 4 -
src/gallium/drivers/radeonsi/si_pipe.c | 1 -
src/gallium/drivers/svga/svga_screen.c | 6 -
src/gallium/drivers/vc4/vc4_screen.c | 2 -
src/gallium/drivers/virgl/virgl_screen.c | 2 -
src/gallium/include/pipe/p_defines.h | 1 -
src/gallium/include/pipe/p_shader_tokens.h | 19 ---
src/gallium/state_trackers/nine/nine_shader.c | 18 +--
35 files changed, 23 insertions(+), 689 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index 7a4c8e4..b8c5c80 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -42,22 +42,20 @@
* Some are slightly above SM 3.0 requirements to give some wiggle room to
* the state trackers.
*/
#define LP_MAX_TGSI_TEMPS 4096
#define LP_MAX_TGSI_ADDRS 16
#define LP_MAX_TGSI_IMMEDIATES 4096
-#define LP_MAX_TGSI_PREDS 16
-
#define LP_MAX_TGSI_CONSTS 4096
#define LP_MAX_TGSI_CONST_BUFFERS 16
#define LP_MAX_TGSI_CONST_BUFFER_SIZE (LP_MAX_TGSI_CONSTS * sizeof(float[4]))
/*
* For quick access we cache registers in statically
* allocated arrays. Here we define the maximum size
* for those arrays.
@@ -102,22 +100,20 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_INPUTS:
return 32;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return LP_MAX_TGSI_CONST_BUFFER_SIZE;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return PIPE_MAX_CONSTANT_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEMPS:
return LP_MAX_TGSI_TEMPS;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return LP_MAX_TGSI_PREDS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 1;
case PIPE_SHADER_CAP_INTEGERS:
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
index b6b3fe3..a9f3d44 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
@@ -451,21 +451,20 @@ struct lp_build_tgsi_soa_context
LLVMValueRef context_ptr;
LLVMValueRef thread_data_ptr;
const struct lp_build_sampler_soa *sampler;
struct tgsi_declaration_sampler_view sv[PIPE_MAX_SHADER_SAMPLER_VIEWS];
LLVMValueRef immediates[LP_MAX_INLINED_IMMEDIATES][TGSI_NUM_CHANNELS];
LLVMValueRef temps[LP_MAX_INLINED_TEMPS][TGSI_NUM_CHANNELS];
LLVMValueRef addr[LP_MAX_TGSI_ADDRS][TGSI_NUM_CHANNELS];
- LLVMValueRef preds[LP_MAX_TGSI_PREDS][TGSI_NUM_CHANNELS];
/* We allocate/use this array of temps if (1 << TGSI_FILE_TEMPORARY) is
* set in the indirect_files field.
* The temps[] array above is unused then.
*/
LLVMValueRef temps_array;
/* We allocate/use this array of output if (1 << TGSI_FILE_OUTPUT) is
* set in the indirect_files field.
* The outputs[] array above is unused then.
@@ -545,21 +544,20 @@ struct lp_build_tgsi_aos_context
const LLVMValueRef *inputs;
LLVMValueRef *outputs;
struct lp_build_sampler_aos *sampler;
struct tgsi_declaration_sampler_view sv[PIPE_MAX_SHADER_SAMPLER_VIEWS];
LLVMValueRef immediates[LP_MAX_INLINED_IMMEDIATES];
LLVMValueRef temps[LP_MAX_INLINED_TEMPS];
LLVMValueRef addr[LP_MAX_TGSI_ADDRS];
- LLVMValueRef preds[LP_MAX_TGSI_PREDS];
/* We allocate/use this array of temps if (1 << TGSI_FILE_TEMPORARY) is
* set in the indirect_files field.
* The temps[] array above is unused then.
*/
LLVMValueRef temps_array;
/** bitmask indicating which register files are accessed indirectly */
unsigned indirect_files;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
index 2bd4291..58c39fa 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c
@@ -249,68 +249,27 @@ lp_emit_store_aos(
break;
case TGSI_FILE_TEMPORARY:
ptr = bld->temps[reg->Register.Index];
break;
case TGSI_FILE_ADDRESS:
ptr = bld->addr[reg->Indirect.Index];
break;
- case TGSI_FILE_PREDICATE:
- ptr = bld->preds[reg->Register.Index];
- break;
-
default:
assert(0);
return;
}
if (!ptr)
return;
- /*
- * Predicate
- */
-
- if (inst->Instruction.Predicate) {
- LLVMValueRef pred;
-
- assert(inst->Predicate.Index < LP_MAX_TGSI_PREDS);
-
- pred = LLVMBuildLoad(builder,
- bld->preds[inst->Predicate.Index], "");
-
- /*
- * Convert the value to an integer mask.
- */
- pred = lp_build_compare(bld->bld_base.base.gallivm,
- bld->bld_base.base.type,
- PIPE_FUNC_NOTEQUAL,
- pred,
- bld->bld_base.base.zero);
-
- if (inst->Predicate.Negate) {
- pred = LLVMBuildNot(builder, pred, "");
- }
-
- pred = bld->bld_base.emit_swizzle(&bld->bld_base, pred,
- inst->Predicate.SwizzleX,
- inst->Predicate.SwizzleY,
- inst->Predicate.SwizzleZ,
- inst->Predicate.SwizzleW);
-
- if (mask) {
- mask = LLVMBuildAnd(builder, mask, pred, "");
- } else {
- mask = pred;
- }
- }
/*
* Writemask
*/
if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
LLVMValueRef writemask;
writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
bld->bld_base.base.type,
@@ -435,25 +394,20 @@ lp_emit_declaration_aos(
case TGSI_FILE_OUTPUT:
bld->outputs[idx] = lp_build_alloca(gallivm, vec_type, "");
break;
case TGSI_FILE_ADDRESS:
assert(idx < LP_MAX_TGSI_ADDRS);
bld->addr[idx] = lp_build_alloca(gallivm, vec_type, "");
break;
- case TGSI_FILE_PREDICATE:
- assert(idx < LP_MAX_TGSI_PREDS);
- bld->preds[idx] = lp_build_alloca(gallivm, vec_type, "");
- break;
-
case TGSI_FILE_SAMPLER_VIEW:
/*
* The target stored here MUST match whatever there actually
* is in the set sampler views (what about return type?).
*/
assert(last < PIPE_MAX_SHADER_SAMPLER_VIEWS);
for (idx = first; idx <= last; ++idx) {
bld->sv[idx] = decl->SamplerView;
}
break;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
index f8f43a5..e0cc0af 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
@@ -298,22 +298,21 @@ analyse_instruction(struct analysis_context *ctx,
* Get the lp_tgsi_channel_info array corresponding to the destination
* register file.
*/
if (dst->File == TGSI_FILE_TEMPORARY) {
regs = ctx->temp;
max_regs = ARRAY_SIZE(ctx->temp);
} else if (dst->File == TGSI_FILE_OUTPUT) {
regs = info->output;
max_regs = ARRAY_SIZE(info->output);
- } else if (dst->File == TGSI_FILE_ADDRESS ||
- dst->File == TGSI_FILE_PREDICATE) {
+ } else if (dst->File == TGSI_FILE_ADDRESS) {
continue;
} else {
assert(0);
continue;
}
/*
* Detect direct TEX instructions
*/
@@ -382,22 +381,21 @@ analyse_instruction(struct analysis_context *ctx,
}
} else if (dst->Index < max_regs) {
/*
* Update this destination register value.
*/
struct lp_tgsi_channel_info res[4];
memset(res, 0, sizeof res);
- if (!inst->Instruction.Predicate &&
- !inst->Instruction.Saturate) {
+ if (!inst->Instruction.Saturate) {
for (chan = 0; chan < 4; ++chan) {
if (dst->WriteMask & (1 << chan)) {
if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
analyse_src(ctx, &res[chan],
&inst->Src[0].Register, chan);
} else if (inst->Instruction.Opcode == TGSI_OPCODE_MUL) {
/*
* Propagate values across 1.0 and 0.0 multiplications.
*/
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 6871795..307adfc 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -746,39 +746,30 @@ static void lp_exec_default(struct lp_exec_mask *mask,
}
/* stores val into an address pointed to by dst_ptr.
* mask->exec_mask is used to figure out which bits of val
* should be stored into the address
* (0 means don't store this bit, 1 means do store).
*/
static void lp_exec_mask_store(struct lp_exec_mask *mask,
struct lp_build_context *bld_store,
- LLVMValueRef pred,
LLVMValueRef val,
LLVMValueRef dst_ptr)
{
LLVMBuilderRef builder = mask->bld->gallivm->builder;
+ LLVMValueRef pred = mask->has_mask ? mask->exec_mask : NULL;
assert(lp_check_value(bld_store->type, val));
assert(LLVMGetTypeKind(LLVMTypeOf(dst_ptr)) == LLVMPointerTypeKind);
assert(LLVMGetElementType(LLVMTypeOf(dst_ptr)) == LLVMTypeOf(val));
- /* Mix the predicate and execution mask */
- if (mask->has_mask) {
- if (pred) {
- pred = LLVMBuildAnd(builder, pred, mask->exec_mask, "");
- } else {
- pred = mask->exec_mask;
- }
- }
-
if (pred) {
LLVMValueRef res, dst;
dst = LLVMBuildLoad(builder, dst_ptr, "");
res = lp_build_select(bld_store, pred, val, dst);
LLVMBuildStore(builder, res, dst_ptr);
} else
LLVMBuildStore(builder, val, dst_ptr);
}
@@ -1029,36 +1020,26 @@ build_gather(struct lp_build_tgsi_context *bld_base,
/**
* Scatter/store vector.
*/
static void
emit_mask_scatter(struct lp_build_tgsi_soa_context *bld,
LLVMValueRef base_ptr,
LLVMValueRef indexes,
LLVMValueRef values,
- struct lp_exec_mask *mask,
- LLVMValueRef pred)
+ struct lp_exec_mask *mask)
{
struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
unsigned i;
-
- /* Mix the predicate and execution mask */
- if (mask->has_mask) {
- if (pred) {
- pred = LLVMBuildAnd(builder, pred, mask->exec_mask, "");
- }
- else {
- pred = mask->exec_mask;
- }
- }
+ LLVMValueRef pred = mask->has_mask ? mask->exec_mask : NULL;
/*
* Loop over elements of index_vec, store scalar value.
*/
for (i = 0; i < bld->bld_base.base.type.length; i++) {
LLVMValueRef ii = lp_build_const_int32(gallivm, i);
LLVMValueRef index = LLVMBuildExtractElement(builder, indexes, ii, "");
LLVMValueRef scalar_ptr = LLVMBuildGEP(builder, base_ptr, &index, 1, "scatter_ptr");
LLVMValueRef val = LLVMBuildExtractElement(builder, values, ii, "scatter_val");
LLVMValueRef scalar_pred = pred ?
@@ -1726,101 +1707,32 @@ emit_fetch_deriv(
/* TODO: use interpolation coeffs for inputs */
if (ddx)
*ddx = lp_build_ddx(&bld->bld_base.base, src);
if (ddy)
*ddy = lp_build_ddy(&bld->bld_base.base, src);
}
-
-/**
- * Predicate.
- */
-static void
-emit_fetch_predicate(
- struct lp_build_tgsi_soa_context *bld,
- const struct tgsi_full_instruction *inst,
- LLVMValueRef *pred)
-{
- LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
- unsigned index;
- unsigned char swizzles[4];
- LLVMValueRef unswizzled[4] = {NULL, NULL, NULL, NULL};
- LLVMValueRef value;
- unsigned chan;
-
- if (!inst->Instruction.Predicate) {
- TGSI_FOR_EACH_CHANNEL( chan ) {
- pred[chan] = NULL;
- }
- return;
- }
-
- swizzles[0] = inst->Predicate.SwizzleX;
- swizzles[1] = inst->Predicate.SwizzleY;
- swizzles[2] = inst->Predicate.SwizzleZ;
- swizzles[3] = inst->Predicate.SwizzleW;
-
- index = inst->Predicate.Index;
- assert(index < LP_MAX_TGSI_PREDS);
-
- TGSI_FOR_EACH_CHANNEL( chan ) {
- unsigned swizzle = swizzles[chan];
-
- /*
- * Only fetch the predicate register channels that are actually listed
- * in the swizzles
- */
- if (!unswizzled[swizzle]) {
- value = LLVMBuildLoad(builder,
- bld->preds[index][swizzle], "");
-
- /*
- * Convert the value to an integer mask.
- *
- * TODO: Short-circuit this comparison -- a D3D setp_xx instructions
- * is needlessly causing two comparisons due to storing the intermediate
- * result as float vector instead of an integer mask vector.
- */
- value = lp_build_compare(bld->bld_base.base.gallivm,
- bld->bld_base.base.type,
- PIPE_FUNC_NOTEQUAL,
- value,
- bld->bld_base.base.zero);
- if (inst->Predicate.Negate) {
- value = LLVMBuildNot(builder, value, "");
- }
-
- unswizzled[swizzle] = value;
- } else {
- value = unswizzled[swizzle];
- }
-
- pred[chan] = value;
- }
-}
-
/**
* store an array of 8 64-bit into two arrays of 8 floats
* i.e.
* value is d0, d1, d2, d3 etc.
* each 64-bit has high and low pieces x, y
* so gets stored into the separate channels as:
* chan_ptr = d0.x, d1.x, d2.x, d3.x
* chan_ptr2 = d0.y, d1.y, d2.y, d3.y
*/
static void
emit_store_64bit_chan(struct lp_build_tgsi_context *bld_base,
LLVMValueRef chan_ptr, LLVMValueRef chan_ptr2,
- LLVMValueRef pred,
LLVMValueRef value)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
struct lp_build_context *float_bld = &bld_base->base;
unsigned i;
LLVMValueRef temp, temp2;
LLVMValueRef shuffles[8];
LLVMValueRef shuffles2[8];
@@ -1834,34 +1746,33 @@ emit_store_64bit_chan(struct lp_build_tgsi_context *bld_base,
LLVMGetUndef(LLVMTypeOf(value)),
LLVMConstVector(shuffles,
bld_base->base.type.length),
"");
temp2 = LLVMBuildShuffleVector(builder, value,
LLVMGetUndef(LLVMTypeOf(value)),
LLVMConstVector(shuffles2,
bld_base->base.type.length),
"");
- lp_exec_mask_store(&bld->exec_mask, float_bld, pred, temp, chan_ptr);
- lp_exec_mask_store(&bld->exec_mask, float_bld, pred, temp2, chan_ptr2);
+ lp_exec_mask_store(&bld->exec_mask, float_bld, temp, chan_ptr);
+ lp_exec_mask_store(&bld->exec_mask, float_bld, temp2, chan_ptr2);
}
/**
* Register store.
*/
static void
emit_store_chan(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
unsigned index,
unsigned chan_index,
- LLVMValueRef pred,
LLVMValueRef value)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_dst_register *reg = &inst->Dst[index];
struct lp_build_context *float_bld = &bld_base->base;
struct lp_build_context *int_bld = &bld_base->int_bld;
LLVMValueRef indirect_index = NULL;
enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
@@ -1910,33 +1821,33 @@ emit_store_chan(
index_vec = get_soa_array_offsets(&bld_base->uint_bld,
indirect_index,
chan_index,
TRUE);
fptr_type = LLVMPointerType(LLVMFloatTypeInContext(gallivm->context), 0);
outputs_array = LLVMBuildBitCast(builder, bld->outputs_array, fptr_type, "");
/* Scatter store values into output registers */
emit_mask_scatter(bld, outputs_array, index_vec, value,
- &bld->exec_mask, pred);
+ &bld->exec_mask);
}
else {
LLVMValueRef out_ptr = lp_get_output_ptr(bld, reg->Register.Index,
chan_index);
if (tgsi_type_is_64bit(dtype)) {
LLVMValueRef out_ptr2 = lp_get_output_ptr(bld, reg->Register.Index,
chan_index + 1);
emit_store_64bit_chan(bld_base, out_ptr, out_ptr2,
- pred, value);
+ value);
} else
- lp_exec_mask_store(&bld->exec_mask, float_bld, pred, value, out_ptr);
+ lp_exec_mask_store(&bld->exec_mask, float_bld, value, out_ptr);
}
break;
case TGSI_FILE_TEMPORARY:
/* Temporaries are always stored as floats */
if (!tgsi_type_is_64bit(dtype))
value = LLVMBuildBitCast(builder, value, float_bld->vec_type, "");
else
value = LLVMBuildBitCast(builder, value, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context), bld_base->base.type.length * 2), "");
@@ -1948,53 +1859,46 @@ emit_store_chan(
index_vec = get_soa_array_offsets(&bld_base->uint_bld,
indirect_index,
chan_index,
TRUE);
fptr_type = LLVMPointerType(LLVMFloatTypeInContext(gallivm->context), 0);
temps_array = LLVMBuildBitCast(builder, bld->temps_array, fptr_type, "");
/* Scatter store values into temp registers */
emit_mask_scatter(bld, temps_array, index_vec, value,
- &bld->exec_mask, pred);
+ &bld->exec_mask);
}
else {
LLVMValueRef temp_ptr;
temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
if (tgsi_type_is_64bit(dtype)) {
LLVMValueRef temp_ptr2 = lp_get_temp_ptr_soa(bld,
reg->Register.Index,
chan_index + 1);
emit_store_64bit_chan(bld_base, temp_ptr, temp_ptr2,
- pred, value);
+ value);
}
else
- lp_exec_mask_store(&bld->exec_mask, float_bld, pred, value, temp_ptr);
+ lp_exec_mask_store(&bld->exec_mask, float_bld, value, temp_ptr);
}
break;
case TGSI_FILE_ADDRESS:
assert(dtype == TGSI_TYPE_SIGNED);
assert(LLVMTypeOf(value) == int_bld->vec_type);
value = LLVMBuildBitCast(builder, value, int_bld->vec_type, "");
- lp_exec_mask_store(&bld->exec_mask, int_bld, pred, value,
+ lp_exec_mask_store(&bld->exec_mask, int_bld, value,
bld->addr[reg->Register.Index][chan_index]);
break;
- case TGSI_FILE_PREDICATE:
- assert(LLVMTypeOf(value) == float_bld->vec_type);
- value = LLVMBuildBitCast(builder, value, float_bld->vec_type, "");
- lp_exec_mask_store(&bld->exec_mask, float_bld, pred, value,
- bld->preds[reg->Register.Index][chan_index]);
- break;
-
default:
assert( 0 );
}
(void)dtype;
}
/*
* Called at the beginning of the translation of each TGSI instruction, to
* emit some debug code.
@@ -2030,32 +1934,28 @@ emit_debug(
static void
emit_store(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_instruction * inst,
const struct tgsi_opcode_info * info,
LLVMValueRef dst[4])
{
unsigned chan_index;
- struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
- if(info->num_dst) {
- LLVMValueRef pred[TGSI_NUM_CHANNELS];
-
- emit_fetch_predicate( bld, inst, pred );
+ if(info->num_dst) {
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
if (tgsi_type_is_64bit(dtype) && (chan_index == 1 || chan_index == 3))
continue;
- emit_store_chan(bld_base, inst, 0, chan_index, pred[chan_index], dst[chan_index]);
+ emit_store_chan(bld_base, inst, 0, chan_index, dst[chan_index]);
}
}
}
static unsigned
tgsi_to_pipe_tex_target(unsigned tgsi_target)
{
switch (tgsi_target) {
case TGSI_TEXTURE_BUFFER:
return PIPE_BUFFER;
@@ -2991,29 +2891,20 @@ lp_emit_declaration_soa(
* an ADDR register for that matter).
*/
assert(last < LP_MAX_TGSI_ADDRS);
for (idx = first; idx <= last; ++idx) {
assert(idx < LP_MAX_TGSI_ADDRS);
for (i = 0; i < TGSI_NUM_CHANNELS; i++)
bld->addr[idx][i] = lp_build_alloca(gallivm, bld_base->base.int_vec_type, "addr");
}
break;
- case TGSI_FILE_PREDICATE:
- assert(last < LP_MAX_TGSI_PREDS);
- for (idx = first; idx <= last; ++idx) {
- for (i = 0; i < TGSI_NUM_CHANNELS; i++)
- bld->preds[idx][i] = lp_build_alloca(gallivm, vec_type,
- "predicate");
- }
- break;
-
case TGSI_FILE_SAMPLER_VIEW:
/*
* The target stored here MUST match whatever there actually
* is in the set sampler views (what about return type?).
*/
assert(last < PIPE_MAX_SHADER_SAMPLER_VIEWS);
for (idx = first; idx <= last; ++idx) {
bld->sv[idx] = decl->SamplerView;
}
break;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 773f892..39c20b5 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -630,111 +630,67 @@ tgsi_build_full_immediate(
struct tgsi_instruction
tgsi_default_instruction( void )
{
struct tgsi_instruction instruction;
instruction.Type = TGSI_TOKEN_TYPE_INSTRUCTION;
instruction.NrTokens = 0;
instruction.Opcode = TGSI_OPCODE_MOV;
instruction.Saturate = 0;
- instruction.Predicate = 0;
instruction.NumDstRegs = 1;
instruction.NumSrcRegs = 1;
instruction.Label = 0;
instruction.Texture = 0;
instruction.Memory = 0;
instruction.Padding = 0;
return instruction;
}
static struct tgsi_instruction
tgsi_build_instruction(unsigned opcode,
unsigned saturate,
- unsigned predicate,
unsigned num_dst_regs,
unsigned num_src_regs,
struct tgsi_header *header)
{
struct tgsi_instruction instruction;
assert (opcode <= TGSI_OPCODE_LAST);
assert (saturate <= 1);
assert (num_dst_regs <= 3);
assert (num_src_regs <= 15);
instruction = tgsi_default_instruction();
instruction.Opcode = opcode;
instruction.Saturate = saturate;
- instruction.Predicate = predicate;
instruction.NumDstRegs = num_dst_regs;
instruction.NumSrcRegs = num_src_regs;
header_bodysize_grow( header );
return instruction;
}
static void
instruction_grow(
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
assert (instruction->NrTokens < 0xFF);
instruction->NrTokens++;
header_bodysize_grow( header );
}
-struct tgsi_instruction_predicate
-tgsi_default_instruction_predicate(void)
-{
- struct tgsi_instruction_predicate instruction_predicate;
-
- instruction_predicate.SwizzleX = TGSI_SWIZZLE_X;
- instruction_predicate.SwizzleY = TGSI_SWIZZLE_Y;
- instruction_predicate.SwizzleZ = TGSI_SWIZZLE_Z;
- instruction_predicate.SwizzleW = TGSI_SWIZZLE_W;
- instruction_predicate.Negate = 0;
- instruction_predicate.Index = 0;
- instruction_predicate.Padding = 0;
-
- return instruction_predicate;
-}
-
-static struct tgsi_instruction_predicate
-tgsi_build_instruction_predicate(int index,
- unsigned negate,
- unsigned swizzleX,
- unsigned swizzleY,
- unsigned swizzleZ,
- unsigned swizzleW,
- struct tgsi_instruction *instruction,
- struct tgsi_header *header)
-{
- struct tgsi_instruction_predicate instruction_predicate;
-
- instruction_predicate = tgsi_default_instruction_predicate();
- instruction_predicate.SwizzleX = swizzleX;
- instruction_predicate.SwizzleY = swizzleY;
- instruction_predicate.SwizzleZ = swizzleZ;
- instruction_predicate.SwizzleW = swizzleW;
- instruction_predicate.Negate = negate;
- instruction_predicate.Index = index;
-
- instruction_grow(instruction, header);
-
- return instruction_predicate;
-}
-
static struct tgsi_instruction_label
tgsi_default_instruction_label( void )
{
struct tgsi_instruction_label instruction_label;
instruction_label.Label = 0;
instruction_label.Padding = 0;
return instruction_label;
}
@@ -1059,21 +1015,20 @@ tgsi_default_full_dst_register( void )
return full_dst_register;
}
struct tgsi_full_instruction
tgsi_default_full_instruction( void )
{
struct tgsi_full_instruction full_instruction;
unsigned i;
full_instruction.Instruction = tgsi_default_instruction();
- full_instruction.Predicate = tgsi_default_instruction_predicate();
full_instruction.Label = tgsi_default_instruction_label();
full_instruction.Texture = tgsi_default_instruction_texture();
full_instruction.Memory = tgsi_default_instruction_memory();
for( i = 0; i < TGSI_FULL_MAX_TEX_OFFSETS; i++ ) {
full_instruction.TexOffsets[i] = tgsi_default_texture_offset();
}
for( i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++ ) {
full_instruction.Dst[i] = tgsi_default_full_dst_register();
}
for( i = 0; i < TGSI_FULL_MAX_SRC_REGISTERS; i++ ) {
@@ -1095,46 +1050,25 @@ tgsi_build_full_instruction(
struct tgsi_instruction *instruction;
struct tgsi_token *prev_token;
if( maxsize <= size )
return 0;
instruction = (struct tgsi_instruction *) &tokens[size];
size++;
*instruction = tgsi_build_instruction(full_inst->Instruction.Opcode,
full_inst->Instruction.Saturate,
- full_inst->Instruction.Predicate,
full_inst->Instruction.NumDstRegs,
full_inst->Instruction.NumSrcRegs,
header);
prev_token = (struct tgsi_token *) instruction;
- if (full_inst->Instruction.Predicate) {
- struct tgsi_instruction_predicate *instruction_predicate;
-
- if (maxsize <= size) {
- return 0;
- }
- instruction_predicate = (struct tgsi_instruction_predicate *)&tokens[size];
- size++;
-
- *instruction_predicate =
- tgsi_build_instruction_predicate(full_inst->Predicate.Index,
- full_inst->Predicate.Negate,
- full_inst->Predicate.SwizzleX,
- full_inst->Predicate.SwizzleY,
- full_inst->Predicate.SwizzleZ,
- full_inst->Predicate.SwizzleW,
- instruction,
- header);
- }
-
if (full_inst->Instruction.Label) {
struct tgsi_instruction_label *instruction_label;
if( maxsize <= size )
return 0;
instruction_label =
(struct tgsi_instruction_label *) &tokens[size];
size++;
*instruction_label = tgsi_build_instruction_label(
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.h b/src/gallium/auxiliary/tgsi/tgsi_build.h
index 34d181a..53f3193 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.h
@@ -103,21 +103,18 @@ tgsi_default_instruction( void );
struct tgsi_full_instruction
tgsi_default_full_instruction( void );
unsigned
tgsi_build_full_instruction(
const struct tgsi_full_instruction *full_inst,
struct tgsi_token *tokens,
struct tgsi_header *header,
unsigned maxsize );
-struct tgsi_instruction_predicate
-tgsi_default_instruction_predicate(void);
-
struct tgsi_full_src_register
tgsi_full_src_register_from_dst(const struct tgsi_full_dst_register *dst);
#if defined __cplusplus
}
#endif
#endif /* TGSI_BUILD_H */
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index 14911c4..a094bdb 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -567,44 +567,20 @@ iter_instruction(
boolean first_reg = TRUE;
INSTID( instno );
TXT( ": " );
ctx->indent -= info->pre_dedent;
for(i = 0; (int)i < ctx->indent; ++i)
TXT( " " );
ctx->indent += info->post_indent;
- if (inst->Instruction.Predicate) {
- CHR( '(' );
-
- if (inst->Predicate.Negate)
- CHR( '!' );
-
- TXT( "PRED[" );
- SID( inst->Predicate.Index );
- CHR( ']' );
-
- if (inst->Predicate.SwizzleX != TGSI_SWIZZLE_X ||
- inst->Predicate.SwizzleY != TGSI_SWIZZLE_Y ||
- inst->Predicate.SwizzleZ != TGSI_SWIZZLE_Z ||
- inst->Predicate.SwizzleW != TGSI_SWIZZLE_W) {
- CHR( '.' );
- ENM( inst->Predicate.SwizzleX, tgsi_swizzle_names );
- ENM( inst->Predicate.SwizzleY, tgsi_swizzle_names );
- ENM( inst->Predicate.SwizzleZ, tgsi_swizzle_names );
- ENM( inst->Predicate.SwizzleW, tgsi_swizzle_names );
- }
-
- TXT( ") " );
- }
-
TXT( info->mnemonic );
if (inst->Instruction.Saturate) {
TXT( "_SAT" );
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (!first_reg)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 48d91af..c41954c 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -1284,21 +1284,20 @@ tgsi_exec_machine_create(enum pipe_shader_type shader_type)
mach = align_malloc( sizeof *mach, 16 );
if (!mach)
goto fail;
memset(mach, 0, sizeof(*mach));
mach->ShaderType = shader_type;
mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
- mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
if (shader_type != PIPE_SHADER_COMPUTE) {
mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
if (!mach->Inputs || !mach->Outputs)
goto fail;
}
/* Setup constants needed by the SSE2 executor. */
for( i = 0; i < 4; i++ ) {
@@ -1552,29 +1551,20 @@ fetch_src_file_channel(const struct tgsi_exec_machine *mach,
case TGSI_FILE_ADDRESS:
for (i = 0; i < TGSI_QUAD_SIZE; i++) {
assert(index->i[i] >= 0);
assert(index2D->i[i] == 0);
chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
}
break;
- case TGSI_FILE_PREDICATE:
- for (i = 0; i < TGSI_QUAD_SIZE; i++) {
- assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
- assert(index2D->i[i] == 0);
-
- chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
- }
- break;
-
case TGSI_FILE_OUTPUT:
/* vertex/fragment output vars can be read too */
for (i = 0; i < TGSI_QUAD_SIZE; i++) {
assert(index->i[i] >= 0);
assert(index2D->i[i] == 0);
chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
}
break;
@@ -1763,25 +1753,23 @@ fetch_source(const struct tgsi_exec_machine *mach,
}
static union tgsi_exec_channel *
store_dest_dstret(struct tgsi_exec_machine *mach,
const union tgsi_exec_channel *chan,
const struct tgsi_full_dst_register *reg,
const struct tgsi_full_instruction *inst,
uint chan_index,
enum tgsi_exec_datatype dst_datatype)
{
- uint i;
static union tgsi_exec_channel null;
union tgsi_exec_channel *dst;
union tgsi_exec_channel index2D;
- uint execmask = mach->ExecMask;
int offset = 0; /* indirection offset */
int index;
/* for debugging */
if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
check_inf_or_nan(chan);
}
/* There is an extra source register that indirectly subscripts
* a register file. The direct index now becomes an offset
@@ -1919,72 +1907,25 @@ store_dest_dstret(struct tgsi_exec_machine *mach,
index = reg->Register.Index;
assert( index < TGSI_EXEC_NUM_TEMPS );
dst = &mach->Temps[offset + index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
index = reg->Register.Index;
dst = &mach->Addrs[index].xyzw[chan_index];
break;
- case TGSI_FILE_PREDICATE:
- index = reg->Register.Index;
- assert(index < TGSI_EXEC_NUM_PREDS);
- dst = &mach->Predicates[index].xyzw[chan_index];
- break;
-
default:
assert( 0 );
return NULL;
}
- if (inst->Instruction.Predicate) {
- uint swizzle;
- union tgsi_exec_channel *pred;
-
- switch (chan_index) {
- case TGSI_CHAN_X:
- swizzle = inst->Predicate.SwizzleX;
- break;
- case TGSI_CHAN_Y:
- swizzle = inst->Predicate.SwizzleY;
- break;
- case TGSI_CHAN_Z:
- swizzle = inst->Predicate.SwizzleZ;
- break;
- case TGSI_CHAN_W:
- swizzle = inst->Predicate.SwizzleW;
- break;
- default:
- assert(0);
- return NULL;
- }
-
- assert(inst->Predicate.Index == 0);
-
- pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
-
- if (inst->Predicate.Negate) {
- for (i = 0; i < TGSI_QUAD_SIZE; i++) {
- if (pred->u[i]) {
- execmask &= ~(1 << i);
- }
- }
- } else {
- for (i = 0; i < TGSI_QUAD_SIZE; i++) {
- if (!pred->u[i]) {
- execmask &= ~(1 << i);
- }
- }
- }
- }
-
return dst;
}
static void
store_dest_double(struct tgsi_exec_machine *mach,
const union tgsi_exec_channel *chan,
const struct tgsi_full_dst_register *reg,
const struct tgsi_full_instruction *inst,
uint chan_index,
enum tgsi_exec_datatype dst_datatype)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index d78b3c8..5708a50 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -266,24 +266,20 @@ struct tgsi_sampler
#define TGSI_EXEC_TEMP_HALF_I (TGSI_EXEC_NUM_TEMPS + 3)
#define TGSI_EXEC_TEMP_HALF_C 0
/* 4 register buffer for various purposes */
#define TGSI_EXEC_TEMP_R0 (TGSI_EXEC_NUM_TEMPS + 4)
#define TGSI_EXEC_NUM_TEMP_R 4
#define TGSI_EXEC_TEMP_ADDR (TGSI_EXEC_NUM_TEMPS + 8)
#define TGSI_EXEC_NUM_ADDRS 3
-/* predicate register */
-#define TGSI_EXEC_TEMP_P0 (TGSI_EXEC_NUM_TEMPS + 11)
-#define TGSI_EXEC_NUM_PREDS 1
-
#define TGSI_EXEC_NUM_TEMP_EXTRAS 12
#define TGSI_EXEC_MAX_NESTING 32
#define TGSI_EXEC_MAX_COND_NESTING TGSI_EXEC_MAX_NESTING
#define TGSI_EXEC_MAX_LOOP_NESTING TGSI_EXEC_MAX_NESTING
#define TGSI_EXEC_MAX_SWITCH_NESTING TGSI_EXEC_MAX_NESTING
#define TGSI_EXEC_MAX_CALL_NESTING TGSI_EXEC_MAX_NESTING
@@ -352,21 +348,20 @@ struct tgsi_exec_machine
float ImmArray[TGSI_EXEC_NUM_IMMEDIATES][4];
struct tgsi_exec_vector *Inputs;
struct tgsi_exec_vector *Outputs;
/* System values */
unsigned SysSemanticToIndex[TGSI_SEMANTIC_COUNT];
struct tgsi_exec_vector SystemValue[TGSI_MAX_MISC_INPUTS];
struct tgsi_exec_vector *Addrs;
- struct tgsi_exec_vector *Predicates;
struct tgsi_sampler *Sampler;
struct tgsi_image *Image;
struct tgsi_buffer *Buffer;
unsigned ImmLimit;
const void *Consts[PIPE_MAX_CONSTANT_BUFFERS];
unsigned ConstsSize[PIPE_MAX_CONSTANT_BUFFERS];
@@ -498,22 +493,20 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_INPUTS:
return TGSI_EXEC_MAX_INPUT_ATTRIBS;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return TGSI_EXEC_MAX_CONST_BUFFER_SIZE;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return PIPE_MAX_CONSTANT_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEMPS:
return TGSI_EXEC_NUM_TEMPS;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return TGSI_EXEC_NUM_PREDS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 1;
case PIPE_SHADER_CAP_INTEGERS:
diff --git a/src/gallium/auxiliary/tgsi/tgsi_parse.c b/src/gallium/auxiliary/tgsi/tgsi_parse.c
index 940af7d..c706fc8 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_parse.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_parse.c
@@ -175,24 +175,20 @@ tgsi_parse_token(
break;
}
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
struct tgsi_full_instruction *inst = &ctx->FullToken.FullInstruction;
memset(inst, 0, sizeof *inst);
copy_token(&inst->Instruction, &token);
- if (inst->Instruction.Predicate) {
- next_token(ctx, &inst->Predicate);
- }
-
if (inst->Instruction.Label) {
next_token( ctx, &inst->Label);
}
if (inst->Instruction.Texture) {
next_token( ctx, &inst->Texture);
for (i = 0; i < inst->Texture.NumOffsets; i++) {
next_token( ctx, &inst->TexOffsets[i] );
}
}
diff --git a/src/gallium/auxiliary/tgsi/tgsi_parse.h b/src/gallium/auxiliary/tgsi/tgsi_parse.h
index 4689fb7..07806ab 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_parse.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_parse.h
@@ -81,21 +81,20 @@ struct tgsi_full_property
struct tgsi_property_data u[8];
};
#define TGSI_FULL_MAX_DST_REGISTERS 2
#define TGSI_FULL_MAX_SRC_REGISTERS 5 /* SAMPLE_D has 5 */
#define TGSI_FULL_MAX_TEX_OFFSETS 4
struct tgsi_full_instruction
{
struct tgsi_instruction Instruction;
- struct tgsi_instruction_predicate Predicate;
struct tgsi_instruction_label Label;
struct tgsi_instruction_texture Texture;
struct tgsi_instruction_memory Memory;
struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
struct tgsi_full_src_register Src[TGSI_FULL_MAX_SRC_REGISTERS];
struct tgsi_texture_offset TexOffsets[TGSI_FULL_MAX_TEX_OFFSETS];
};
union tgsi_full_token
{
diff --git a/src/gallium/auxiliary/tgsi/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
index 239a2c9..a95bbfa 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_sanity.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
@@ -249,21 +249,20 @@ is_ind_register_used(
static const char *file_names[TGSI_FILE_COUNT] =
{
"NULL",
"CONST",
"IN",
"OUT",
"TEMP",
"SAMP",
"ADDR",
"IMM",
- "PRED",
"SV",
"RES"
};
static boolean
check_register_usage(
struct sanity_check_ctx *ctx,
scan_register *reg,
const char *name,
boolean indirect_access )
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index cebc1b4..8bc789d 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -45,21 +45,20 @@ const char *tgsi_processor_type_names[6] =
static const char *tgsi_file_names[] =
{
"NULL",
"CONST",
"IN",
"OUT",
"TEMP",
"SAMP",
"ADDR",
"IMM",
- "PRED",
"SV",
"IMAGE",
"SVIEW",
"BUFFER",
"MEMORY",
};
const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
{
"POSITION",
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 4ed9050..93a0556 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1029,57 +1029,20 @@ parse_instruction(
{
uint i;
uint saturate = 0;
const struct tgsi_opcode_info *info;
struct tgsi_full_instruction inst;
const char *cur;
uint advance;
inst = tgsi_default_full_instruction();
- /* Parse predicate.
- */
- eat_opt_white( &ctx->cur );
- if (*ctx->cur == '(') {
- uint file;
- int index;
- uint swizzle[4];
- boolean parsed_swizzle;
-
- inst.Instruction.Predicate = 1;
-
- ctx->cur++;
- if (*ctx->cur == '!') {
- ctx->cur++;
- inst.Predicate.Negate = 1;
- }
-
- if (!parse_register_1d( ctx, &file, &index ))
- return FALSE;
-
- if (parse_optional_swizzle( ctx, swizzle, &parsed_swizzle, 4 )) {
- if (parsed_swizzle) {
- inst.Predicate.SwizzleX = swizzle[0];
- inst.Predicate.SwizzleY = swizzle[1];
- inst.Predicate.SwizzleZ = swizzle[2];
- inst.Predicate.SwizzleW = swizzle[3];
- }
- }
-
- if (*ctx->cur != ')') {
- report_error( ctx, "Expected `)'" );
- return FALSE;
- }
-
- ctx->cur++;
- }
-
/* Parse instruction name.
*/
eat_opt_white( &ctx->cur );
for (i = 0; i < TGSI_OPCODE_LAST; i++) {
cur = ctx->cur;
info = tgsi_get_opcode_info( i );
if (match_inst(&cur, &saturate, info)) {
if (info->num_dst + info->num_src + info->is_tex == 0) {
ctx->cur = cur;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index ab0a3eb..9eb00d0 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -50,21 +50,20 @@ union tgsi_any_token {
struct tgsi_declaration_range decl_range;
struct tgsi_declaration_dimension decl_dim;
struct tgsi_declaration_interp decl_interp;
struct tgsi_declaration_image decl_image;
struct tgsi_declaration_semantic decl_semantic;
struct tgsi_declaration_sampler_view decl_sampler_view;
struct tgsi_declaration_array array;
struct tgsi_immediate imm;
union tgsi_immediate_data imm_data;
struct tgsi_instruction insn;
- struct tgsi_instruction_predicate insn_predicate;
struct tgsi_instruction_label insn_label;
struct tgsi_instruction_texture insn_texture;
struct tgsi_instruction_memory insn_memory;
struct tgsi_texture_offset insn_texture_offset;
struct tgsi_src_register src;
struct tgsi_ind_register ind;
struct tgsi_dimension dim;
struct tgsi_dst_register dst;
unsigned value;
};
@@ -76,21 +75,20 @@ struct ureg_tokens {
unsigned order;
unsigned count;
};
#define UREG_MAX_INPUT (4 * PIPE_MAX_SHADER_INPUTS)
#define UREG_MAX_SYSTEM_VALUE PIPE_MAX_ATTRIBS
#define UREG_MAX_OUTPUT (4 * PIPE_MAX_SHADER_OUTPUTS)
#define UREG_MAX_CONSTANT_RANGE 32
#define UREG_MAX_IMMEDIATE 4096
#define UREG_MAX_ADDR 3
-#define UREG_MAX_PRED 1
#define UREG_MAX_ARRAY_TEMPS 256
struct const_decl {
struct {
unsigned first;
unsigned last;
} constant_range[UREG_MAX_CONSTANT_RANGE];
unsigned nr_constant_ranges;
};
@@ -181,21 +179,20 @@ struct ureg_program
unsigned array_temps[UREG_MAX_ARRAY_TEMPS];
unsigned nr_array_temps;
struct const_decl const_decls;
struct const_decl const_decls2D[PIPE_MAX_CONSTANT_BUFFERS];
unsigned properties[TGSI_PROPERTY_COUNT];
unsigned nr_addrs;
- unsigned nr_preds;
unsigned nr_instructions;
struct ureg_tokens domain[2];
bool use_memory[TGSI_MEMORY_TYPE_COUNT];
};
static union tgsi_any_token error_tokens[32];
static void tokens_error( struct ureg_tokens *tokens )
@@ -256,20 +253,21 @@ static union tgsi_any_token *get_tokens( struct ureg_program *ureg,
static union tgsi_any_token *retrieve_token( struct ureg_program *ureg,
unsigned domain,
unsigned nr )
{
if (ureg->domain[domain].tokens == error_tokens)
return &error_tokens[0];
return &ureg->domain[domain].tokens[nr];
}
+
void
ureg_property(struct ureg_program *ureg, unsigned name, unsigned value)
{
assert(name < ARRAY_SIZE(ureg->properties));
ureg->properties[name] = value;
}
struct ureg_src
ureg_DECL_fs_input_cyl_centroid_layout(struct ureg_program *ureg,
unsigned semantic_name,
@@ -664,33 +662,20 @@ void ureg_release_temporary( struct ureg_program *ureg,
*/
struct ureg_dst ureg_DECL_address( struct ureg_program *ureg )
{
if (ureg->nr_addrs < UREG_MAX_ADDR)
return ureg_dst_register( TGSI_FILE_ADDRESS, ureg->nr_addrs++ );
assert( 0 );
return ureg_dst_register( TGSI_FILE_ADDRESS, 0 );
}
-/* Allocate a new predicate register.
- */
-struct ureg_dst
-ureg_DECL_predicate(struct ureg_program *ureg)
-{
- if (ureg->nr_preds < UREG_MAX_PRED) {
- return ureg_dst_register(TGSI_FILE_PREDICATE, ureg->nr_preds++);
- }
-
- assert(0);
- return ureg_dst_register(TGSI_FILE_PREDICATE, 0);
-}
-
/* Allocate a new sampler.
*/
struct ureg_src ureg_DECL_sampler( struct ureg_program *ureg,
unsigned nr )
{
unsigned i;
for (i = 0; i < ureg->nr_samplers; i++)
if (ureg->sampler[i].Index == nr)
return ureg->sampler[i];
@@ -1221,55 +1206,39 @@ static void validate( unsigned opcode,
assert(nr_dst == info->num_dst);
assert(nr_src == info->num_src);
}
#endif
}
struct ureg_emit_insn_result
ureg_emit_insn(struct ureg_program *ureg,
unsigned opcode,
boolean saturate,
- boolean predicate,
- boolean pred_negate,
- unsigned pred_swizzle_x,
- unsigned pred_swizzle_y,
- unsigned pred_swizzle_z,
- unsigned pred_swizzle_w,
unsigned num_dst,
- unsigned num_src )
+ unsigned num_src)
{
union tgsi_any_token *out;
- uint count = predicate ? 2 : 1;
+ uint count = 1;
struct ureg_emit_insn_result result;
validate( opcode, num_dst, num_src );
out = get_tokens( ureg, DOMAIN_INSN, count );
out[0].insn = tgsi_default_instruction();
out[0].insn.Opcode = opcode;
out[0].insn.Saturate = saturate;
out[0].insn.NumDstRegs = num_dst;
out[0].insn.NumSrcRegs = num_src;
result.insn_token = ureg->domain[DOMAIN_INSN].count - count;
result.extended_token = result.insn_token;
- if (predicate) {
- out[0].insn.Predicate = 1;
- out[1].insn_predicate = tgsi_default_instruction_predicate();
- out[1].insn_predicate.Negate = pred_negate;
- out[1].insn_predicate.SwizzleX = pred_swizzle_x;
- out[1].insn_predicate.SwizzleY = pred_swizzle_y;
- out[1].insn_predicate.SwizzleZ = pred_swizzle_z;
- out[1].insn_predicate.SwizzleW = pred_swizzle_w;
- }
-
ureg->nr_instructions++;
return result;
}
/**
* Emit a label token.
* \param label_token returns a token number indicating where the label
* needs to be patched later. Later, this value should be passed to the
@@ -1382,47 +1351,30 @@ void
ureg_insn(struct ureg_program *ureg,
unsigned opcode,
const struct ureg_dst *dst,
unsigned nr_dst,
const struct ureg_src *src,
unsigned nr_src )
{
struct ureg_emit_insn_result insn;
unsigned i;
boolean saturate;
- boolean predicate;
- boolean negate = FALSE;
- unsigned swizzle[4] = { 0 };
if (nr_dst && ureg_dst_is_empty(dst[0])) {
return;
}
saturate = nr_dst ? dst[0].Saturate : FALSE;
- predicate = nr_dst ? dst[0].Predicate : FALSE;
- if (predicate) {
- negate = dst[0].PredNegate;
- swizzle[0] = dst[0].PredSwizzleX;
- swizzle[1] = dst[0].PredSwizzleY;
- swizzle[2] = dst[0].PredSwizzleZ;
- swizzle[3] = dst[0].PredSwizzleW;
- }
insn = ureg_emit_insn(ureg,
opcode,
saturate,
- predicate,
- negate,
- swizzle[0],
- swizzle[1],
- swizzle[2],
- swizzle[3],
nr_dst,
nr_src);
for (i = 0; i < nr_dst; i++)
ureg_emit_dst( ureg, dst[i] );
for (i = 0; i < nr_src; i++)
ureg_emit_src( ureg, src[i] );
ureg_fixup_insn_size( ureg, insn.insn_token );
@@ -1435,47 +1387,30 @@ ureg_tex_insn(struct ureg_program *ureg,
unsigned nr_dst,
unsigned target,
const struct tgsi_texture_offset *texoffsets,
unsigned nr_offset,
const struct ureg_src *src,
unsigned nr_src )
{
struct ureg_emit_insn_result insn;
unsigned i;
boolean saturate;
- boolean predicate;
- boolean negate = FALSE;
- unsigned swizzle[4] = { 0 };
if (nr_dst && ureg_dst_is_empty(dst[0])) {
return;
}
saturate = nr_dst ? dst[0].Saturate : FALSE;
- predicate = nr_dst ? dst[0].Predicate : FALSE;
- if (predicate) {
- negate = dst[0].PredNegate;
- swizzle[0] = dst[0].PredSwizzleX;
- swizzle[1] = dst[0].PredSwizzleY;
- swizzle[2] = dst[0].PredSwizzleZ;
- swizzle[3] = dst[0].PredSwizzleW;
- }
insn = ureg_emit_insn(ureg,
opcode,
saturate,
- predicate,
- negate,
- swizzle[0],
- swizzle[1],
- swizzle[2],
- swizzle[3],
nr_dst,
nr_src);
ureg_emit_texture( ureg, insn.extended_token, target, nr_offset );
for (i = 0; i < nr_offset; i++)
ureg_emit_texture_offset( ureg, &texoffsets[i]);
for (i = 0; i < nr_dst; i++)
ureg_emit_dst( ureg, dst[i] );
@@ -1497,26 +1432,20 @@ ureg_memory_insn(struct ureg_program *ureg,
unsigned qualifier,
unsigned texture,
unsigned format)
{
struct ureg_emit_insn_result insn;
unsigned i;
insn = ureg_emit_insn(ureg,
opcode,
FALSE,
- FALSE,
- FALSE,
- TGSI_SWIZZLE_X,
- TGSI_SWIZZLE_Y,
- TGSI_SWIZZLE_Z,
- TGSI_SWIZZLE_W,
nr_dst,
nr_src);
ureg_emit_memory(ureg, insn.extended_token, qualifier, texture, format);
for (i = 0; i < nr_dst; i++)
ureg_emit_dst(ureg, dst[i]);
for (i = 0; i < nr_src; i++)
ureg_emit_src(ureg, src[i]);
@@ -1995,27 +1924,20 @@ static void emit_decls( struct ureg_program *ureg )
emit_decl_temps( ureg, first, i - 1, local, 0 );
}
}
if (ureg->nr_addrs) {
emit_decl_range( ureg,
TGSI_FILE_ADDRESS,
0, ureg->nr_addrs );
}
- if (ureg->nr_preds) {
- emit_decl_range(ureg,
- TGSI_FILE_PREDICATE,
- 0,
- ureg->nr_preds);
- }
-
for (i = 0; i < ureg->nr_immediates; i++) {
emit_immediate( ureg,
ureg->immediate[i].value.u,
ureg->immediate[i].type );
}
}
/* Append the instruction tokens onto the declarations to build a
* contiguous stream suitable to send to the driver.
*/
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index 99908d9..d301915 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -72,26 +72,20 @@ struct ureg_src
* instruction function.
*/
struct ureg_dst
{
unsigned File : 4; /* TGSI_FILE_ */
unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
unsigned Indirect : 1; /* BOOL */
unsigned DimIndirect : 1; /* BOOL */
unsigned Dimension : 1; /* BOOL */
unsigned Saturate : 1; /* BOOL */
- unsigned Predicate : 1;
- unsigned PredNegate : 1; /* BOOL */
- unsigned PredSwizzleX : 2; /* TGSI_SWIZZLE_ */
- unsigned PredSwizzleY : 2; /* TGSI_SWIZZLE_ */
- unsigned PredSwizzleZ : 2; /* TGSI_SWIZZLE_ */
- unsigned PredSwizzleW : 2; /* TGSI_SWIZZLE_ */
int Index : 16; /* SINT */
int IndirectIndex : 16; /* SINT */
unsigned IndirectFile : 4; /* TGSI_FILE_ */
int IndirectSwizzle : 2; /* TGSI_SWIZZLE_ */
unsigned DimIndFile : 4; /* TGSI_FILE_ */
unsigned DimIndSwizzle : 2; /* TGSI_SWIZZLE_ */
int DimensionIndex : 16; /* SINT */
int DimIndIndex : 16; /* SINT */
unsigned ArrayID : 10; /* UINT */
};
@@ -341,23 +335,20 @@ ureg_DECL_array_temporary( struct ureg_program *,
unsigned size,
boolean local );
void
ureg_release_temporary( struct ureg_program *ureg,
struct ureg_dst tmp );
struct ureg_dst
ureg_DECL_address( struct ureg_program * );
-struct ureg_dst
-ureg_DECL_predicate(struct ureg_program *);
-
/* Supply an index to the sampler declaration as this is the hook to
* the external pipe_sampler state. Users of this function probably
* don't want just any sampler, but a specific one which they've set
* up state for in the context.
*/
struct ureg_src
ureg_DECL_sampler( struct ureg_program *,
unsigned index );
struct ureg_src
@@ -587,28 +578,22 @@ ureg_memory_insn(struct ureg_program *ureg,
struct ureg_emit_insn_result {
unsigned insn_token; /*< Used to fixup insn size. */
unsigned extended_token; /*< Used to set the Extended bit, usually the same as insn_token. */
};
struct ureg_emit_insn_result
ureg_emit_insn(struct ureg_program *ureg,
unsigned opcode,
boolean saturate,
- boolean predicate,
- boolean pred_negate,
- unsigned pred_swizzle_x,
- unsigned pred_swizzle_y,
- unsigned pred_swizzle_z,
- unsigned pred_swizzle_w,
unsigned num_dst,
- unsigned num_src );
+ unsigned num_src);
void
ureg_emit_label(struct ureg_program *ureg,
unsigned insn_token,
unsigned *label_token );
void
ureg_emit_texture(struct ureg_program *ureg,
unsigned insn_token,
unsigned target, unsigned num_offsets);
@@ -638,164 +623,122 @@ ureg_fixup_insn_size(struct ureg_program *ureg,
#define OP00( op ) \
static inline void ureg_##op( struct ureg_program *ureg ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
insn = ureg_emit_insn(ureg, \
opcode, \
FALSE, \
- FALSE, \
- FALSE, \
- TGSI_SWIZZLE_X, \
- TGSI_SWIZZLE_Y, \
- TGSI_SWIZZLE_Z, \
- TGSI_SWIZZLE_W, \
0, \
0); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP01( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
insn = ureg_emit_insn(ureg, \
opcode, \
FALSE, \
- FALSE, \
- FALSE, \
- TGSI_SWIZZLE_X, \
- TGSI_SWIZZLE_Y, \
- TGSI_SWIZZLE_Z, \
- TGSI_SWIZZLE_W, \
0, \
1); \
ureg_emit_src( ureg, src ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP00_LBL( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
unsigned *label_token ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
insn = ureg_emit_insn(ureg, \
opcode, \
FALSE, \
- FALSE, \
- FALSE, \
- TGSI_SWIZZLE_X, \
- TGSI_SWIZZLE_Y, \
- TGSI_SWIZZLE_Z, \
- TGSI_SWIZZLE_W, \
0, \
0); \
ureg_emit_label( ureg, insn.extended_token, label_token ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP01_LBL( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src, \
unsigned *label_token ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
insn = ureg_emit_insn(ureg, \
opcode, \
FALSE, \
- FALSE, \
- FALSE, \
- TGSI_SWIZZLE_X, \
- TGSI_SWIZZLE_Y, \
- TGSI_SWIZZLE_Z, \
- TGSI_SWIZZLE_W, \
0, \
1); \
ureg_emit_label( ureg, insn.extended_token, label_token ); \
ureg_emit_src( ureg, src ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP10( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_dst dst ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
0); \
ureg_emit_dst( ureg, dst ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP11( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_dst dst, \
struct ureg_src src ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
1); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP12( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_dst dst, \
struct ureg_src src0, \
struct ureg_src src1 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
2); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP12_TEX( op ) \
static inline void ureg_##op( struct ureg_program *ureg, \
@@ -804,26 +747,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src0, \
struct ureg_src src1 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
2); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP12_SAMPLE( op ) \
@@ -833,26 +770,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src1 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
unsigned target = TGSI_TEXTURE_UNKNOWN; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
2); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP13( op ) \
@@ -862,26 +793,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src1, \
struct ureg_src src2 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
3); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
#define OP13_SAMPLE( op ) \
@@ -892,26 +817,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src2 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
unsigned target = TGSI_TEXTURE_UNKNOWN; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
3); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
@@ -924,26 +843,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src2, \
struct ureg_src src3 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
4); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_emit_src( ureg, src3 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
@@ -957,26 +870,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src3 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
unsigned target = TGSI_TEXTURE_UNKNOWN; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
4); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_emit_src( ureg, src3 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
@@ -990,26 +897,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src2, \
struct ureg_src src3 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
4); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_emit_src( ureg, src3 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
@@ -1023,26 +924,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src3, \
struct ureg_src src4 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
5); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_emit_src( ureg, src3 ); \
ureg_emit_src( ureg, src4 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
}
@@ -1057,26 +952,20 @@ static inline void ureg_##op( struct ureg_program *ureg, \
struct ureg_src src4 ) \
{ \
unsigned opcode = TGSI_OPCODE_##op; \
unsigned target = TGSI_TEXTURE_UNKNOWN; \
struct ureg_emit_insn_result insn; \
if (ureg_dst_is_empty(dst)) \
return; \
insn = ureg_emit_insn(ureg, \
opcode, \
dst.Saturate, \
- dst.Predicate, \
- dst.PredNegate, \
- dst.PredSwizzleX, \
- dst.PredSwizzleY, \
- dst.PredSwizzleZ, \
- dst.PredSwizzleW, \
1, \
5); \
ureg_emit_texture( ureg, insn.extended_token, target, 0 ); \
ureg_emit_dst( ureg, dst ); \
ureg_emit_src( ureg, src0 ); \
ureg_emit_src( ureg, src1 ); \
ureg_emit_src( ureg, src2 ); \
ureg_emit_src( ureg, src3 ); \
ureg_emit_src( ureg, src4 ); \
ureg_fixup_insn_size( ureg, insn.insn_token ); \
@@ -1146,38 +1035,20 @@ ureg_writemask( struct ureg_dst reg,
}
static inline struct ureg_dst
ureg_saturate( struct ureg_dst reg )
{
assert(reg.File != TGSI_FILE_NULL);
reg.Saturate = 1;
return reg;
}
-static inline struct ureg_dst
-ureg_predicate(struct ureg_dst reg,
- boolean negate,
- unsigned swizzle_x,
- unsigned swizzle_y,
- unsigned swizzle_z,
- unsigned swizzle_w)
-{
- assert(reg.File != TGSI_FILE_NULL);
- reg.Predicate = 1;
- reg.PredNegate = negate;
- reg.PredSwizzleX = swizzle_x;
- reg.PredSwizzleY = swizzle_y;
- reg.PredSwizzleZ = swizzle_z;
- reg.PredSwizzleW = swizzle_w;
- return reg;
-}
-
static inline struct ureg_dst
ureg_dst_indirect( struct ureg_dst reg, struct ureg_src addr )
{
assert(reg.File != TGSI_FILE_NULL);
assert(addr.File == TGSI_FILE_ADDRESS || addr.File == TGSI_FILE_TEMPORARY);
reg.Indirect = 1;
reg.IndirectFile = addr.File;
reg.IndirectIndex = addr.Index;
reg.IndirectSwizzle = addr.SwizzleX;
return reg;
@@ -1264,26 +1135,20 @@ ureg_dst_array_register(unsigned file,
{
struct ureg_dst dst;
dst.File = file;
dst.WriteMask = TGSI_WRITEMASK_XYZW;
dst.Indirect = 0;
dst.IndirectFile = TGSI_FILE_NULL;
dst.IndirectIndex = 0;
dst.IndirectSwizzle = 0;
dst.Saturate = 0;
- dst.Predicate = 0;
- dst.PredNegate = 0;
- dst.PredSwizzleX = TGSI_SWIZZLE_X;
- dst.PredSwizzleY = TGSI_SWIZZLE_Y;
- dst.PredSwizzleZ = TGSI_SWIZZLE_Z;
- dst.PredSwizzleW = TGSI_SWIZZLE_W;
dst.Index = index;
dst.Dimension = 0;
dst.DimensionIndex = 0;
dst.DimIndirect = 0;
dst.DimIndFile = TGSI_FILE_NULL;
dst.DimIndIndex = 0;
dst.DimIndSwizzle = 0;
dst.ArrayID = array_id;
return dst;
@@ -1305,26 +1170,20 @@ ureg_dst( struct ureg_src src )
(src.IndirectFile == TGSI_FILE_ADDRESS ||
src.IndirectFile == TGSI_FILE_TEMPORARY));
dst.File = src.File;
dst.WriteMask = TGSI_WRITEMASK_XYZW;
dst.IndirectFile = src.IndirectFile;
dst.Indirect = src.Indirect;
dst.IndirectIndex = src.IndirectIndex;
dst.IndirectSwizzle = src.IndirectSwizzle;
dst.Saturate = 0;
- dst.Predicate = 0;
- dst.PredNegate = 0;
- dst.PredSwizzleX = TGSI_SWIZZLE_X;
- dst.PredSwizzleY = TGSI_SWIZZLE_Y;
- dst.PredSwizzleZ = TGSI_SWIZZLE_Z;
- dst.PredSwizzleW = TGSI_SWIZZLE_W;
dst.Index = src.Index;
dst.Dimension = src.Dimension;
dst.DimensionIndex = src.DimensionIndex;
dst.DimIndirect = src.DimIndirect;
dst.DimIndFile = src.DimIndFile;
dst.DimIndIndex = src.DimIndIndex;
dst.DimIndSwizzle = src.DimIndSwizzle;
dst.ArrayID = src.ArrayID;
return dst;
@@ -1402,26 +1261,20 @@ ureg_dst_undef( void )
{
struct ureg_dst dst;
dst.File = TGSI_FILE_NULL;
dst.WriteMask = 0;
dst.Indirect = 0;
dst.IndirectFile = TGSI_FILE_NULL;
dst.IndirectIndex = 0;
dst.IndirectSwizzle = 0;
dst.Saturate = 0;
- dst.Predicate = 0;
- dst.PredNegate = 0;
- dst.PredSwizzleX = TGSI_SWIZZLE_X;
- dst.PredSwizzleY = TGSI_SWIZZLE_Y;
- dst.PredSwizzleZ = TGSI_SWIZZLE_Z;
- dst.PredSwizzleW = TGSI_SWIZZLE_W;
dst.Index = 0;
dst.Dimension = 0;
dst.DimensionIndex = 0;
dst.DimIndirect = 0;
dst.DimIndFile = TGSI_FILE_NULL;
dst.DimIndIndex = 0;
dst.DimIndSwizzle = 0;
dst.ArrayID = 0;
return dst;
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index 00c9503..dc698a7 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -427,21 +427,20 @@ be accessed with two-dimensional indices, like in the example below.
DCL CONST[0][0..7] # declare first 8 vectors of constbuf 0
DCL CONST[3][0] # declare first vector of constbuf 3
MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0
For backwards compatibility, one-dimensional access to CONST register
file is still supported. In that case, the constbuf index is assumed
to be 0.
* ``PIPE_SHADER_CAP_MAX_TEMPS``: The maximum number of temporary registers.
-* ``PIPE_SHADER_CAP_MAX_PREDS``: The maximum number of predicate registers.
* ``PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED``: Whether the continue opcode is supported.
* ``PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR``: Whether indirect addressing
of the input file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR``: Whether indirect addressing
of the output file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR``: Whether indirect addressing
of the temporary file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_CONST_ADDR``: Whether indirect addressing
of the constant file is supported.
* ``PIPE_SHADER_CAP_SUBROUTINES``: Whether subroutines are supported, i.e.
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 5657de5..712c58d 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -468,22 +468,20 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEMPS:
return 64; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
/* NOTE: seems to be limit for a3xx is actually 512 but
* split between VS and FS. Use lower limit of 256 to
* avoid getting into impossible situations:
*/
return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return is_ir3(screen) ? 16 : 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
/* Technically this should be the same as for TEMP/CONST, since
* everything is just normal registers. This is just temporary
* hack until load_input/store_output handle arrays in a similar
* way as load_var/store_var..
*/
return 0;
diff --git a/src/gallium/drivers/i915/i915_fpc.h b/src/gallium/drivers/i915/i915_fpc.h
index adc4254..309cf8e 100644
--- a/src/gallium/drivers/i915/i915_fpc.h
+++ b/src/gallium/drivers/i915/i915_fpc.h
@@ -289,21 +289,20 @@ struct i915_full_src_register
struct tgsi_ind_register Indirect;
struct tgsi_dimension Dimension;
struct tgsi_ind_register DimIndirect;
*/
};
struct i915_full_instruction
{
struct tgsi_instruction Instruction;
/*
- struct tgsi_instruction_predicate Predicate;
struct tgsi_instruction_label Label;
*/
struct tgsi_instruction_texture Texture;
struct i915_full_dst_register Dst[1];
struct i915_full_src_register Src[3];
};
union i915_full_token
{
diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c
index d25c2b3..0ae49c6 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -139,22 +139,20 @@ i915_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_INPUTS:
return 10;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 1;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 32 * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 12; /* XXX: 12 -> 32 ? */
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 7aaeedf..13625bf 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -406,21 +406,20 @@ nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
}
static nv50_ir::DataFile translateFile(uint file)
{
switch (file) {
case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
- case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
case TGSI_FILE_BUFFER: return nv50_ir::FILE_MEMORY_BUFFER;
case TGSI_FILE_IMAGE: return nv50_ir::FILE_MEMORY_GLOBAL;
case TGSI_FILE_MEMORY: return nv50_ir::FILE_MEMORY_GLOBAL;
case TGSI_FILE_SAMPLER:
case TGSI_FILE_NULL:
default:
return nv50_ir::FILE_NULL;
}
@@ -1477,21 +1476,20 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
case TGSI_FILE_TEMPORARY:
for (i = first; i <= last; ++i)
tempArrayId[i] = arrayId;
if (arrayId)
tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
first, last - first + 1)));
break;
case TGSI_FILE_ADDRESS:
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
- case TGSI_FILE_PREDICATE:
case TGSI_FILE_SAMPLER:
case TGSI_FILE_BUFFER:
break;
default:
ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
return false;
}
return true;
}
@@ -1738,21 +1736,20 @@ private:
uint ip; // instruction pointer
tgsi::Instruction tgsi;
DataType dstTy;
DataType srcTy;
DataArray tData; // TGSI_FILE_TEMPORARY
DataArray lData; // TGSI_FILE_TEMPORARY, for indirect arrays
DataArray aData; // TGSI_FILE_ADDRESS
- DataArray pData; // TGSI_FILE_PREDICATE
DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
Value *zero;
Value *fragCoord[4];
Value *clipVtx[4];
Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
uint8_t vtxBaseValid;
Value *outBase; // base address of vertex out patch (for TCP)
@@ -1961,22 +1958,20 @@ Converter::fetchSrc(int s, int c)
return applySrcMod(res, s, c);
}
Converter::DataArray *
Converter::getArrayForFile(unsigned file, int idx)
{
switch (file) {
case TGSI_FILE_TEMPORARY:
return idx == 0 ? &tData : &lData;
- case TGSI_FILE_PREDICATE:
- return &pData;
case TGSI_FILE_ADDRESS:
return &aData;
case TGSI_FILE_OUTPUT:
assert(prog->getType() == Program::TYPE_FRAGMENT);
return &oData;
default:
assert(!"invalid/unhandled TGSI source file");
return NULL;
}
}
@@ -2131,21 +2126,20 @@ Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
exported at EMIT time */
if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
viewport != NULL)
mkOp1(OP_MOV, TYPE_U32, viewport, val);
else
mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
info->out[idx].patch;
}
} else
if (f == TGSI_FILE_TEMPORARY ||
- f == TGSI_FILE_PREDICATE ||
f == TGSI_FILE_ADDRESS ||
f == TGSI_FILE_OUTPUT) {
if (f == TGSI_FILE_TEMPORARY) {
int arrayid = dst.getArrayId();
if (!arrayid)
arrayid = code->tempArrayId[idx];
adjustTempIndex(arrayid, idx, idx2d);
}
getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
@@ -4190,32 +4184,30 @@ Converter::exportOutputs()
mkOp1(OP_SAT, TYPE_F32, val, val);
mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
}
}
}
}
Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
code(code),
tgsi(NULL),
- tData(this), lData(this), aData(this), pData(this), oData(this)
+ tData(this), lData(this), aData(this), oData(this)
{
info = code->info;
const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
- const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, FILE_GPR, 0);
lData.setup(TGSI_FILE_TEMPORARY, 1, 0, tSize, 4, 4, FILE_MEMORY_LOCAL, 0);
- pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
zero = mkImm((uint32_t)0);
vtxBaseValid = 0;
}
Converter::~Converter()
{
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 5c7ae24..5df4435 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -286,21 +286,20 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 0;
- case PIPE_SHADER_CAP_MAX_PREDS:
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
@@ -334,21 +333,20 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 32;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
- case PIPE_SHADER_CAP_MAX_PREDS:
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 249947a..dc1f6ee 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -319,22 +319,20 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 65536;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return NV50_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_MAX_TEMPS:
return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0; /* please inline, or provide function declarations */
case PIPE_SHADER_CAP_INTEGERS:
return 1;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index cfe4f67..fbd6392 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -359,22 +359,20 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 65536;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return NVC0_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_MAX_TEMPS:
return NVC0_CAP_MAX_PROGRAM_TEMPS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 1;
case PIPE_SHADER_CAP_INTEGERS:
return 1;
diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
index 07a09d5..06ec379 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -323,22 +323,20 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
return 10;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 4;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return (is_r500 ? 256 : 32) * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return is_r500 ? 128 : is_r400 ? 64 : 32;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* unused */
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return r300screen->caps.num_tex_units;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
@@ -382,22 +380,20 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_INPUTS:
return 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 10;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 256 * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 32;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* unused */
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 869f941..8b171bf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -532,22 +532,20 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_const_buffer_size);
return MIN2(max_const_buffer_size, INT_MAX);
} else {
return R600_MAX_CONST_BUFFER_SIZE;
}
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return R600_MAX_USER_CONST_BUFFERS;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 41fabf3..bdaf28c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -390,24 +390,20 @@ static int tgsi_last_instruction(unsigned writemask)
static int tgsi_is_supported(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
unsigned j;
if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
return -EINVAL;
}
- if (i->Instruction.Predicate) {
- R600_ERR("predicate unsupported\n");
- return -EINVAL;
- }
#if 0
if (i->Instruction.Label) {
R600_ERR("label unsupported\n");
return -EINVAL;
}
#endif
for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
if (i->Src[j].Register.Dimension) {
switch (i->Src[j].Register.File) {
case TGSI_FILE_CONSTANT:
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 5af5fdf..71ead62 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -653,21 +653,20 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* TODO: Indirection of geometry shader input dimension is not
* handled yet
*/
return shader != PIPE_SHADER_GEOMETRY;
/* Unsupported and disabled features. */
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
- case PIPE_SHADER_CAP_MAX_PREDS:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_SUPPORTED_IRS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
return 0;
}
return 0;
}
static void si_destroy_screen(struct pipe_screen* pscreen)
diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index cb48ac5..28e76df 100644
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -473,22 +473,20 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
return MIN2(val, SVGA3D_TEMPREG_MAX);
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/*
* Although PS 3.0 has some addressing abilities it can only represent
* loops that can be statically determined and unrolled. Given we can
* only handle a subset of the cases that the state tracker already
* does it is better to defer loop unrolling to the state tracker.
*/
return 0;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 0;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
@@ -532,22 +530,20 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
return 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 10;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 256 * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
return MIN2(val, SVGA3D_TEMPREG_MAX);
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return 0;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
@@ -638,22 +634,20 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return svgascreen->max_const_buffers;
case PIPE_SHADER_CAP_MAX_TEMPS:
return VGPU10_MAX_TEMPS;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return TRUE; /* XXX verify */
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:
return TRUE;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return SVGA3D_DX_MAX_SAMPLERS;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c
index b53e71d..b0242bf 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -368,22 +368,20 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_INPUTS:
return 8;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 16 * 1024 * sizeof(float);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return 0;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index eb6b125..db55abc 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -303,22 +303,20 @@ virgl_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
// case PIPE_SHADER_CAP_MAX_CONSTS:
// return 4096;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return vscreen->caps.caps.v1.max_uniform_blocks;
// case PIPE_SHADER_CAP_MAX_ADDRS:
// return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_SUBROUTINES:
return 1;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
return 16;
case PIPE_SHADER_CAP_INTEGERS:
return vscreen->caps.caps.v1.glsl_level >= 130;
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 32;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 4096 * sizeof(float[4]);
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 924711d..86be005 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -795,21 +795,20 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
PIPE_SHADER_CAP_MAX_INPUTS,
PIPE_SHADER_CAP_MAX_OUTPUTS,
PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
PIPE_SHADER_CAP_MAX_TEMPS,
- PIPE_SHADER_CAP_MAX_PREDS,
/* boolean caps */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
PIPE_SHADER_CAP_INTEGERS,
PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
PIPE_SHADER_CAP_PREFERRED_IR,
diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h
index 6a3fb98..87d2d92 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -62,21 +62,20 @@ struct tgsi_token
enum tgsi_file_type {
TGSI_FILE_NULL,
TGSI_FILE_CONSTANT,
TGSI_FILE_INPUT,
TGSI_FILE_OUTPUT,
TGSI_FILE_TEMPORARY,
TGSI_FILE_SAMPLER,
TGSI_FILE_ADDRESS,
TGSI_FILE_IMMEDIATE,
- TGSI_FILE_PREDICATE,
TGSI_FILE_SYSTEM_VALUE,
TGSI_FILE_IMAGE,
TGSI_FILE_SAMPLER_VIEW,
TGSI_FILE_BUFFER,
TGSI_FILE_MEMORY,
TGSI_FILE_COUNT, /**< how many TGSI_FILE_ types */
};
#define TGSI_WRITEMASK_NONE 0x00
@@ -609,34 +608,31 @@ struct tgsi_property_data {
/**
* Opcode is the operation code to execute. A given operation defines the
* semantics how the source registers (if any) are interpreted and what is
* written to the destination registers (if any) as a result of execution.
*
* NumDstRegs and NumSrcRegs is the number of destination and source registers,
* respectively. For a given operation code, those numbers are fixed and are
* present here only for convenience.
*
- * If Predicate is TRUE, tgsi_instruction_predicate token immediately follows.
- *
* Saturate controls how are final results in destination registers modified.
*/
struct tgsi_instruction
{
unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */
unsigned NrTokens : 8; /* UINT */
unsigned Opcode : 8; /* TGSI_OPCODE_ */
unsigned Saturate : 1; /* BOOL */
unsigned NumDstRegs : 2; /* UINT */
unsigned NumSrcRegs : 4; /* UINT */
- unsigned Predicate : 1; /* BOOL */
unsigned Label : 1;
unsigned Texture : 1;
unsigned Memory : 1;
unsigned Padding : 1;
};
/*
* If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows.
*
* If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows.
@@ -702,35 +698,20 @@ struct tgsi_instruction_texture
struct tgsi_texture_offset
{
int Index : 16;
unsigned File : 4; /**< one of TGSI_FILE_x */
unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */
unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */
unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */
unsigned Padding : 6;
};
-/*
- * For SM3, the following constraint applies.
- * - Swizzle is either set to identity or replicate.
- */
-struct tgsi_instruction_predicate
-{
- int Index : 16; /* SINT */
- unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */
- unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */
- unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */
- unsigned SwizzleW : 2; /* TGSI_SWIZZLE_x */
- unsigned Negate : 1; /* BOOL */
- unsigned Padding : 7;
-};
-
/**
* File specifies the register array to access.
*
* Index specifies the element number of a register in the register file.
*
* If Indirect is TRUE, Index should be offset by the X component of the indirect
* register that follows. The register can be now fetched into local storage
* for further processing.
*
* If Negate is TRUE, all components of the fetched register are negated.
diff --git a/src/gallium/state_trackers/nine/nine_shader.c b/src/gallium/state_trackers/nine/nine_shader.c
index 7760a1c..6dcd976 100644
--- a/src/gallium/state_trackers/nine/nine_shader.c
+++ b/src/gallium/state_trackers/nine/nine_shader.c
@@ -449,21 +449,20 @@ struct shader_translator
BYTE major;
BYTE minor;
} version;
unsigned processor; /* PIPE_SHADER_VERTEX/FRAMGENT */
unsigned num_constf_allowed;
unsigned num_consti_allowed;
unsigned num_constb_allowed;
boolean native_integers;
boolean inline_subroutines;
- boolean lower_preds;
boolean want_texcoord;
boolean shift_wpos;
boolean wpos_is_sysval;
boolean face_is_sysval_integer;
unsigned texcoord_sn;
struct sm1_instruction insn; /* current instruction */
struct {
struct ureg_dst *r;
@@ -728,28 +727,20 @@ tx_temp_alloc(struct shader_translator *tx, INT idx)
static inline void
tx_addr_alloc(struct shader_translator *tx, INT idx)
{
assert(idx == 0);
if (ureg_dst_is_undef(tx->regs.address))
tx->regs.address = ureg_DECL_address(tx->ureg);
if (ureg_dst_is_undef(tx->regs.a0))
tx->regs.a0 = ureg_DECL_temporary(tx->ureg);
}
-static inline void
-tx_pred_alloc(struct shader_translator *tx, INT idx)
-{
- assert(idx == 0);
- if (ureg_dst_is_undef(tx->regs.p))
- tx->regs.p = ureg_DECL_predicate(tx->ureg);
-}
-
/* NOTE: It's not very clear on which ps1.1-ps1.3 instructions
* the projection should be applied on the texture. It doesn't
* apply on texkill.
* The doc is very imprecise here (it says the projection is done
* before rasterization, thus in vs, which seems wrong since ps instructions
* are affected differently)
* For now we only apply to the ps TEX instruction and TEXBEM.
* Perhaps some other instructions would need it */
static inline void
apply_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst,
@@ -977,23 +968,21 @@ tx_src_param(struct shader_translator *tx, const struct sm1_src_param *param)
}
src = ureg_src_array_offset(tx->regs.v_consecutive, param->idx);
} else {
assert(param->idx < ARRAY_SIZE(tx->regs.v));
src = tx->regs.v[param->idx];
}
}
}
break;
case D3DSPR_PREDICATE:
- assert(!param->rel);
- tx_pred_alloc(tx, param->idx);
- src = ureg_src(tx->regs.p);
+ assert(!"D3DSPR_PREDICATE");
break;
case D3DSPR_SAMPLER:
assert(param->mod == NINED3DSPSM_NONE);
assert(param->swizzle == NINED3DSP_NOSWIZZLE);
assert(!param->rel);
src = ureg_src_register(TGSI_FILE_SAMPLER, param->idx);
break;
case D3DSPR_CONST:
assert(!param->rel || IS_VS);
if (param->rel)
@@ -1298,23 +1287,21 @@ _tx_dst_param(struct shader_translator *tx, const struct sm1_dst_param *param)
break;
case D3DSPR_DEPTHOUT:
assert(!param->rel);
if (ureg_dst_is_undef(tx->regs.oDepth))
tx->regs.oDepth =
ureg_DECL_output_masked(tx->ureg, TGSI_SEMANTIC_POSITION, 0,
TGSI_WRITEMASK_Z, 0, 1);
dst = tx->regs.oDepth; /* XXX: must write .z component */
break;
case D3DSPR_PREDICATE:
- assert(!param->rel);
- tx_pred_alloc(tx, param->idx);
- dst = tx->regs.p;
+ assert(!"D3DSPR_PREDICATE");
break;
case D3DSPR_TEMPFLOAT16:
DBG("unhandled D3DSPR: %u\n", param->file);
break;
default:
assert(!"invalid dst D3DSPR");
break;
}
if (param->rel)
dst = ureg_dst_indirect(dst, tx_src_param(tx, param->rel));
@@ -3514,21 +3501,20 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info,
tx->version.major, tx->version.minor);
tx->ureg = ureg_create(processor);
if (!tx->ureg) {
hr = E_OUTOFMEMORY;
goto out;
}
tx->native_integers = GET_SHADER_CAP(INTEGERS);
tx->inline_subroutines = !GET_SHADER_CAP(SUBROUTINES);
- tx->lower_preds = !GET_SHADER_CAP(MAX_PREDS);
tx->want_texcoord = GET_CAP(TGSI_TEXCOORD);
tx->shift_wpos = !GET_CAP(TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
tx->texcoord_sn = tx->want_texcoord ?
TGSI_SEMANTIC_TEXCOORD : TGSI_SEMANTIC_GENERIC;
tx->wpos_is_sysval = GET_CAP(TGSI_FS_POSITION_IS_SYSVAL);
tx->face_is_sysval_integer = GET_CAP(TGSI_FS_FACE_IS_INTEGER_SYSVAL);
if (IS_VS) {
tx->num_constf_allowed = NINE_MAX_CONST_F;
} else if (tx->version.major < 2) {/* IS_PS v1 */
--
2.7.4
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