[Mesa-dev] [PATCH 2/3] nvc0/ir: Handle TGSI_OPCODE_CLOCK

Boyan Ding boyan.j.ding at gmail.com
Fri Mar 31 06:07:16 UTC 2017


2017-03-31 11:24 GMT+08:00 Ilia Mirkin <imirkin at alum.mit.edu>:
> On Thu, Mar 30, 2017 at 10:33 PM, Boyan Ding <boyan.j.ding at gmail.com> wrote:
>> Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
>> ---
>>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> index 7aaeedf8dd..9fbd3c0d30 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -3410,6 +3410,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>           mkCvt(OP_CVT, TYPE_U32, dst0[c], TYPE_U8, val0);
>>        }
>>        break;
>> +   case TGSI_OPCODE_CLOCK:
>> +      // The shifting is weird, but that's how they made it
>> +      mkOp1(OP_RDSV, TYPE_U32, dst0[1], mkSysVal(SV_CLOCK, 0))->fixed = 1;
>> +      mkOp1(OP_RDSV, TYPE_U32, dst0[0], mkSysVal(SV_CLOCK, 1))->fixed = 1;
>
> How sure are you about this? Shouldn't clocklo go into dst[0] and
> clockhi go into dst[1]? This is confirmed by
>
> """
> clock2x32ARB() returns
>     the same value encoded as a two-component vector of 32-bit unsigned integers
>     with the first component containing the 32 least significant bits and the
>     second component containing the 32 most significant bits.
> """
>
> Did the tests fail without that? Perhaps that indicates something else is wrong?

I just noticed there are some issues with clock2x32ARB, wil check it
more carefully.

>
>> +      break;
>>     case TGSI_OPCODE_KILL_IF:
>>        val0 = new_LValue(func, FILE_PREDICATE);
>>        mask = 0;
>> --
>> 2.12.0
>>
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