[Mesa-dev] [PATCH 01/10] radeonsi: adjust checking for SC bug workarounds

[Nicolai Hähnle]

On 30.03.2017 19:15, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> no change in behavior, just making sure that no later chips will use
> the workarounds

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>


> ---
>  src/gallium/drivers/radeonsi/si_pipe.c  |  4 ++++
>  src/gallium/drivers/radeonsi/si_pipe.h  |  1 +
>  src/gallium/drivers/radeonsi/si_state.c | 12 ++++++++----
>  3 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 18b56fa..c32546f 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -835,20 +835,24 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
>  		(sscreen->b.chip_class == CIK &&
>  		 sscreen->b.info.pfp_fw_version >= 211 &&
>  		 sscreen->b.info.me_fw_version >= 173) ||
>  		(sscreen->b.chip_class == SI &&
>  		 sscreen->b.info.pfp_fw_version >= 121 &&
>  		 sscreen->b.info.me_fw_version >= 87);
>
>  	sscreen->has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
>  				   sscreen->b.chip_class >= VI;
>
> +	sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
> +					    sscreen->b.family <= CHIP_POLARIS12) ||
> +					   sscreen->b.family == CHIP_VEGA10;
> +
>  	sscreen->b.has_cp_dma = true;
>  	sscreen->b.has_streamout = true;
>
>  	/* Some chips have RB+ registers, but don't support RB+. Those must
>  	 * always disable it.
>  	 */
>  	if (sscreen->b.family == CHIP_STONEY ||
>  	    sscreen->b.chip_class >= GFX9) {
>  		sscreen->b.has_rbplus = true;
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index 3a6503a..9225899 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -72,20 +72,21 @@ struct si_compute;
>  struct hash_table;
>  struct u_suballocator;
>
>  struct si_screen {
>  	struct r600_common_screen	b;
>  	unsigned			gs_table_depth;
>  	unsigned			tess_offchip_block_dw_size;
>  	bool				has_distributed_tess;
>  	bool				has_draw_indirect_multi;
>  	bool				has_ds_bpermute;
> +	bool				has_msaa_sample_loc_bug;
>
>  	/* Whether shaders are monolithic (1-part) or separate (3-part). */
>  	bool				use_monolithic_shaders;
>  	bool				record_llvm_ir;
>
>  	mtx_t			shader_parts_mutex;
>  	struct si_shader_part		*vs_prologs;
>  	struct si_shader_part		*vs_epilogs;
>  	struct si_shader_part		*tcs_epilogs;
>  	struct si_shader_part		*gs_prologs;
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index f8c6faf..78d6996 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -914,21 +914,21 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
>  		(struct si_state_rasterizer*)sctx->queued.named.rasterizer;
>  	struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
>
>  	if (!state)
>  		return;
>
>  	if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
>  		si_mark_atom_dirty(sctx, &sctx->db_render_state);
>
>  		/* Update the small primitive filter workaround if necessary. */
> -		if (sctx->b.family >= CHIP_POLARIS10 &&
> +		if (sctx->screen->has_msaa_sample_loc_bug &&
>  		    sctx->framebuffer.nr_samples > 1)
>  			si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
>  	}
>
>  	r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
>
>  	si_pm4_bind_state(sctx, rasterizer, rs);
>  	si_update_poly_offset_state(sctx);
>
>  	si_mark_atom_dirty(sctx, &sctx->clip_regs);
> @@ -2854,50 +2854,54 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
>
>  	sctx->framebuffer.dirty_cbufs = 0;
>  	sctx->framebuffer.dirty_zsbuf = false;
>  }
>
>  static void si_emit_msaa_sample_locs(struct si_context *sctx,
>  				     struct r600_atom *atom)
>  {
>  	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
>  	unsigned nr_samples = sctx->framebuffer.nr_samples;
> +	bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
>
>  	/* Smoothing (only possible with nr_samples == 1) uses the same
>  	 * sample locations as the MSAA it simulates.
>  	 */
>  	if (nr_samples <= 1 && sctx->smoothing_enabled)
>  		nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
>
>  	/* On Polaris, the small primitive filter uses the sample locations
>  	 * even when MSAA is off, so we need to make sure they're set to 0.
>  	 */
> -	if (sctx->b.family >= CHIP_POLARIS10)
> +	if (has_msaa_sample_loc_bug)
>  		nr_samples = MAX2(nr_samples, 1);
>
>  	if (nr_samples >= 1 &&
>  	    (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
>  		sctx->msaa_sample_locs.nr_samples = nr_samples;
>  		cayman_emit_msaa_sample_locs(cs, nr_samples);
>  	}
>
>  	if (sctx->b.family >= CHIP_POLARIS10) {
>  		struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
>  		unsigned small_prim_filter_cntl =
>  			S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
> -			S_028830_LINE_FILTER_DISABLE(sctx->b.chip_class == VI); /* line bug */
> +			/* line bug */
> +			S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
>
>  		/* The alternative of setting sample locations to 0 would
>  		 * require a DB flush to avoid Z errors, see
>  		 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
>  		 */
> -		if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
> +		if (has_msaa_sample_loc_bug &&
> +		    sctx->framebuffer.nr_samples > 1 &&
> +		    rs && !rs->multisample_enable)
>  			small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
>
>  		radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
>  				       small_prim_filter_cntl);
>  	}
>  }
>
>  static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
>  {
>  	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
>


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