[Mesa-dev] [PATCH v03 07/38] genxml: 3DSTATE_VS rename Function Enable to Enable.
Rafael Antognolli
rafael.antognolli at intel.com
Tue May 2 01:42:55 UTC 2017
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml | 2 +-
src/intel/genxml/gen8.xml | 2 +-
src/intel/genxml/gen9.xml | 2 +-
src/intel/vulkan/genX_pipeline.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 0bde2d2..bc829d0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -432,7 +432,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
if (vs_prog_data) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
vs.KernelStartPointer = params->vs_prog_kernel;
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 14d643c..a12e22c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1391,7 +1391,7 @@
<field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
<field name="Statistics Enable" start="170" end="170" type="bool"/>
<field name="Vertex Cache Disable" start="161" end="161" type="bool"/>
- <field name="Function Enable" start="160" end="160" type="bool"/>
+ <field name="Enable" start="160" end="160" type="bool"/>
</instruction>
<instruction name="3DSTATE_WM" bias="2" length="9">
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index e6b61b7..2ac096e 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1864,7 +1864,7 @@
<field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
<field name="Statistics Enable" start="170" end="170" type="bool"/>
<field name="Vertex Cache Disable" start="161" end="161" type="bool"/>
- <field name="Function Enable" start="160" end="160" type="bool"/>
+ <field name="Enable" start="160" end="160" type="bool"/>
</instruction>
<instruction name="3DSTATE_WM" bias="2" length="3">
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index e63979c..6d2bfaa 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2192,7 +2192,7 @@
<field name="Maximum Number of Threads" start="183" end="191" type="uint"/>
<field name="Statistics Enable" start="170" end="170" type="bool"/>
<field name="Vertex Cache Disable" start="161" end="161" type="bool"/>
- <field name="Function Enable" start="160" end="160" type="bool"/>
+ <field name="Enable" start="160" end="160" type="bool"/>
</instruction>
<instruction name="3DSTATE_WM" bias="2" length="3">
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 3b44406..05e228c 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2352,7 +2352,7 @@
<field name="Statistics Enable" start="234" end="234" type="bool"/>
<field name="SIMD8 Dispatch Enable" start="226" end="226" type="bool"/>
<field name="Vertex Cache Disable" start="225" end="225" type="bool"/>
- <field name="Function Enable" start="224" end="224" type="bool"/>
+ <field name="Enable" start="224" end="224" type="bool"/>
<field name="Vertex URB Entry Output Read Offset" start="277" end="282" type="uint"/>
<field name="Vertex URB Entry Output Length" start="272" end="276" type="uint"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="264" end="271" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index d78a321..191c74c 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2585,7 +2585,7 @@
<field name="Statistics Enable" start="234" end="234" type="bool"/>
<field name="SIMD8 Dispatch Enable" start="226" end="226" type="bool"/>
<field name="Vertex Cache Disable" start="225" end="225" type="bool"/>
- <field name="Function Enable" start="224" end="224" type="bool"/>
+ <field name="Enable" start="224" end="224" type="bool"/>
<field name="Vertex URB Entry Output Read Offset" start="277" end="282" type="uint"/>
<field name="Vertex URB Entry Output Length" start="272" end="276" type="uint"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="264" end="271" type="uint"/>
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2631ed0..74d6f9a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1132,7 +1132,7 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
vs.StatisticsEnable = true;
vs.KernelStartPointer = vs_bin->kernel.offset;
#if GEN_GEN >= 8
--
git-series 0.9.1
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