[Mesa-dev] [v2 19/39] intel/isl/gen6: Add size calculator for back-to-back layouts
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed May 3 09:22:32 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/intel/isl/isl.c | 26 ++++++++++++++++++--------
src/intel/isl/isl.h | 6 ++++++
src/intel/isl/isl_gen6.c | 27 +++++++++++++++++++++++++++
3 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index e06bb94..e21ef06 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1351,9 +1351,6 @@ isl_surf_init_s(const struct isl_device *dev,
assert(phys_level0_sa.w % fmtl->bw == 0);
assert(phys_level0_sa.h % fmtl->bh == 0);
- enum isl_array_pitch_span array_pitch_span =
- isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
-
struct isl_extent2d phys_slice0_sa;
isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout,
&image_align_sa, &phys_level0_sa,
@@ -1361,12 +1358,25 @@ isl_surf_init_s(const struct isl_device *dev,
assert(phys_slice0_sa.w % fmtl->bw == 0);
assert(phys_slice0_sa.h % fmtl->bh == 0);
- const uint32_t array_pitch_el_rows =
- isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout,
- array_pitch_span, &image_align_sa,
- &phys_level0_sa, &phys_slice0_sa);
+ enum isl_array_pitch_span array_pitch_span;
+ uint32_t array_pitch_el_rows;
+ uint32_t total_h_el;
- uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
+ if (isl_surf_needs_back_to_back_layout(dev, tiling)) {
+ array_pitch_span = 0;
+ array_pitch_el_rows = 0;
+ total_h_el = isl_gen6_calc_back_to_back_total_h(
+ &phys_level0_sa, &image_align_sa,
+ dim_layout, tiling, info->levels);
+ } else {
+ array_pitch_span = isl_choose_array_pitch_span(dev, info, dim_layout,
+ &phys_level0_sa);
+ array_pitch_el_rows = isl_calc_array_pitch_el_rows(
+ dev, info, &tile_info, dim_layout,
+ array_pitch_span, &image_align_sa,
+ &phys_level0_sa, &phys_slice0_sa);
+ total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
+ }
uint32_t pad_bytes;
isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes);
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 3685ddf..d1ea0d5 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1492,6 +1492,12 @@ get_image_offset_sa_gen6_back_to_back(const struct isl_surf *surf,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
+uint32_t
+isl_gen6_calc_back_to_back_total_h(const struct isl_extent4d *phys_level0_sa,
+ const struct isl_extent3d *image_align_sa,
+ enum isl_dim_layout dim_layout,
+ enum isl_tiling tiling, uint32_t levels);
+
/**
* Calculate the offset, in units of surface samples, to a subimage in the
* surface.
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index 8bd5dbc..19430e9 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -191,3 +191,30 @@ get_image_offset_sa_gen6_back_to_back(const struct isl_surf *surf,
*x_offset_sa = 0;
*y_offset_sa = y;
}
+
+uint32_t
+isl_gen6_calc_back_to_back_total_h(const struct isl_extent4d *phys_level0_sa,
+ const struct isl_extent3d *image_align_sa,
+ enum isl_dim_layout dim_layout,
+ enum isl_tiling tiling, uint32_t levels)
+{
+ assert(tiling == ISL_TILING_W ||
+ tiling == ISL_TILING_HIZ);
+ const uint32_t tile_align_h = tiling == ISL_TILING_W ? 64 : 32;
+
+ uint32_t total_h = 0;
+ for (unsigned i = 0; i < levels; ++i) {
+ const unsigned d = dim_layout == ISL_DIM_LAYOUT_GEN4_3D ?
+ isl_minify(phys_level0_sa->depth, i) :
+ phys_level0_sa->array_len;
+ const unsigned h = isl_minify(phys_level0_sa->height, i);
+ total_h += d * isl_align_npot(h, image_align_sa->h);
+
+ /* Align on tile boundary so that driver can offset without intra-tile
+ * offsets.
+ */
+ total_h = isl_align(total_h, tile_align_h);
+ }
+
+ return total_h;
+}
--
2.9.3
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