[Mesa-dev] [v2 25/39] i965: Prepare blit engine for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/intel_blit.c | 37 +++++++++++++++++++++++++---------
 src/mesa/drivers/dri/i965/intel_blit.h | 13 ++++++++++++
 2 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 4cd86dd..be6a851 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -131,6 +131,10 @@ set_blitter_tiling(struct brw_context *brw,
 static int
 blt_pitch(struct intel_mipmap_tree *mt)
 {
+   if (mt->surf.size > 0)
+      return (mt->surf.tiling != ISL_TILING_LINEAR) ?
+             mt->surf.row_pitch / 4 : mt->surf.row_pitch;
+
    int pitch = mt->pitch;
    if (mt->tiling)
       pitch /= 4;
@@ -171,9 +175,13 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
                              uint32_t *x_offset_el,
                              uint32_t *y_offset_el)
 {
+   const unsigned cpp = mt->surf.size > 0 ?
+      isl_format_get_layout(mt->surf.format)->bpb / 8 : mt->cpp;
+   const unsigned pitch = mt->surf.size > 0 ? mt->surf.row_pitch : mt->pitch;
+
    enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
    isl_tiling_get_intratile_offset_el(&brw->isl_dev,
-                                      tiling, mt->cpp, mt->pitch,
+                                      tiling, cpp, pitch,
                                       total_x_offset_el, total_y_offset_el,
                                       base_address_offset,
                                       x_offset_el, y_offset_el);
@@ -188,11 +196,11 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
        * The offsets we get from ISL in the tiled case are already aligned.
        * In the linear case, we need to do some of our own aligning.
        */
-      assert(mt->pitch % 64 == 0);
+      assert(pitch % 64 == 0);
       uint32_t delta = *base_address_offset & 63;
-      assert(delta % mt->cpp == 0);
+      assert(delta % cpp == 0);
       *base_address_offset -= delta;
-      *x_offset_el += delta / mt->cpp;
+      *x_offset_el += delta / cpp;
    } else {
       assert(*base_address_offset % 4096 == 0);
    }
@@ -207,6 +215,17 @@ emit_miptree_blit(struct brw_context *brw,
                   uint32_t width, uint32_t height,
                   bool reverse, GLenum logicop)
 {
+   const unsigned src_cpp = src_mt->surf.size > 0 ?
+      isl_format_get_layout(src_mt->surf.format)->bpb / 8 : src_mt->cpp;
+   const unsigned src_pitch =
+      src_mt->surf.size > 0 ? src_mt->surf.row_pitch : src_mt->pitch;
+   const unsigned dst_pitch =
+      dst_mt->surf.size > 0 ? dst_mt->surf.row_pitch : dst_mt->pitch;
+   const unsigned src_tiling = src_mt->surf.size > 0 ?
+      isl_tiling_to_bufmgr_tiling(src_mt->surf.tiling) : src_mt->tiling;
+   const unsigned dst_tiling = dst_mt->surf.size > 0 ?
+      isl_tiling_to_bufmgr_tiling(dst_mt->surf.tiling) : dst_mt->tiling;
+
    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
     * Data Size Limitations):
     *
@@ -251,13 +270,13 @@ emit_miptree_blit(struct brw_context *brw,
                                       &dst_offset, &dst_tile_x, &dst_tile_y);
 
          if (!intelEmitCopyBlit(brw,
-                                src_mt->cpp,
-                                reverse ? -src_mt->pitch : src_mt->pitch,
+                                src_cpp,
+                                reverse ? -src_pitch : src_pitch,
                                 src_mt->bo, src_mt->offset + src_offset,
-                                src_mt->tiling,
-                                dst_mt->pitch,
+                                src_tiling,
+                                dst_pitch,
                                 dst_mt->bo, dst_mt->offset + dst_offset,
-                                dst_mt->tiling,
+                                dst_tiling,
                                 src_tile_x, src_tile_y,
                                 dst_tile_x, dst_tile_y,
                                 chunk_w, chunk_h,
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h
index 2604417..5e4d1f5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -28,6 +28,19 @@
 
 #include "brw_context.h"
 
+static inline unsigned
+isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
+{
+   if (tiling == ISL_TILING_X)
+      return I915_TILING_X;
+
+   if (tiling == ISL_TILING_Y0)
+      return I915_TILING_Y;
+
+   /* All other are unknown to buffer allocator. */
+   return I915_TILING_NONE;
+}
+
 bool
 intelEmitCopyBlit(struct brw_context *brw,
                   GLuint cpp,
-- 
2.9.3