[Mesa-dev] [v2 28/39] i965: Prepare tex, img and rt state emission for isl based miptrees
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed May 3 09:22:41 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 25 +++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 59415e1..3f6f15e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -138,12 +138,16 @@ brw_emit_surface_state(struct brw_context *brw,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
{
- uint32_t tile_x;
- uint32_t tile_y;
- uint32_t offset;
+ uint32_t tile_x = 0;
+ uint32_t tile_y = 0;
+ uint32_t offset = 0;
struct isl_surf surf;
- get_isl_surf(brw, mt, target, &view, &tile_x, &tile_y, &offset, &surf);
+ if (mt->surf.size > 0) {
+ surf = mt->surf;
+ } else {
+ get_isl_surf(brw, mt, target, &view, &tile_x, &tile_y, &offset, &surf);
+ }
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
@@ -557,9 +561,16 @@ brw_update_texture_surface(struct gl_context *ctx,
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
- const unsigned view_num_layers =
- (obj->Immutable && obj->Target != GL_TEXTURE_3D) ? obj->NumLayers :
- mt->logical_depth0;
+ unsigned view_num_layers;
+ if (obj->Immutable && obj->Target != GL_TEXTURE_3D) {
+ view_num_layers = obj->NumLayers;
+ } else if (mt->surf.size > 0) {
+ view_num_layers = mt->surf.dim_layout == ISL_DIM_LAYOUT_GEN4_3D ?
+ mt->surf.logical_level0_px.depth :
+ mt->surf.logical_level0_px.array_len;
+ } else {
+ view_num_layers = mt->logical_depth0;
+ }
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
--
2.9.3
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