[Mesa-dev] [v2 34/39] i965/gen7: Prepare depth state emission for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/gen7_misc_state.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 8e87222..f3ecab3 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    case GL_TEXTURE_3D:
       assert(mt);
-      depth = MAX2(mt->logical_depth0, 1);
+      depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+                                  MAX2(mt->logical_depth0, 1);
       /* fallthrough */
    default:
       surftype = translate_tex_target(gl_target);
@@ -94,7 +95,16 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
 
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
-   if (mt) {
+   unsigned pitch = 0;
+   if (depth_mt && depth_mt->surf.size > 0)
+      pitch = depth_mt->surf.row_pitch;
+   else if (depth_mt)
+      pitch = depth_mt->pitch;
+
+   if (mt && mt->surf.size > 0) {
+      width = mt->surf.logical_level0_px.width;
+      height = mt->surf.logical_level0_px.height;
+   } else if (mt) {
       width = mt->logical_width0;
       height = mt->logical_height0;
    }
@@ -105,7 +115,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
    /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((pitch ? pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((hiz ? 1 : 0) << 22) |
              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
@@ -165,6 +175,12 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
+      if (stencil_mt->surf.size > 0) {
+         pitch = stencil_mt->surf.row_pitch;
+      } else {
+         pitch = 2 * stencil_mt->pitch;
+      }
+
       stencil_mt->r8stencil_needs_update = true;
       const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
 
@@ -180,9 +196,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
        * While the Ivybridge PRM lacks this comment, the BSpec contains the
        * same text, and experiments indicate that this is necessary.
        */
-      OUT_BATCH(enabled |
-                mocs << 25 |
-	        (2 * stencil_mt->pitch - 1));
+      OUT_BATCH(enabled | mocs << 25 | (pitch - 1));
       OUT_RELOC(stencil_mt->bo,
 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		0);
-- 
2.9.3