[Mesa-dev] [v2 37/39] intel/isl/gen7/hack: Use stencil vertical alignment of 8 instead of 4

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/intel/isl/isl_gen7.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 18687b5..cf5b377 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -375,7 +375,11 @@ gen7_choose_valign_el(const struct isl_device *dev,
        * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API
        * is more polished.
        */
-      require_valign4 = true;
+
+      /* Using valign 4 upsets all depthstencil-render-miplevels on IVB and
+       * HSW. Use alignment 8 instead.
+       */
+      return 8;
    }
 
    assert(!require_valign2 || !require_valign4);
-- 
2.9.3