[Mesa-dev] [PATCH 4/4] radeonsi: clarify documentation of existing SI workaround

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Limiting LS-HS to a single wave is required on all SI chips due to an
issue with a power management feature.
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 3d1d1f8..f31d5c2 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -177,22 +177,24 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	/* Make sure the output data fits in the offchip buffer */
 	*num_patches = MIN2(*num_patches,
 			    (sctx->screen->tess_offchip_block_dw_size * 4) /
 			    output_patch_size);
 
 	/* Not necessary for correctness, but improves performance. The
 	 * specific value is taken from the proprietary driver.
 	 */
 	*num_patches = MIN2(*num_patches, 40);
 
-	/* SI bug workaround - limit LS-HS threadgroups to only one wave. */
 	if (sctx->b.chip_class == SI) {
+		/* SI bug workaround, related to power management. Limit LS-HS
+		 * threadgroups to only one wave.
+		 */
 		unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
 		*num_patches = MIN2(*num_patches, one_wave);
 
 		if (sctx->screen->b.info.max_se == 1) {
 			/* The VGT HS block increments the patch ID unconditionally
 			 * within a single threadgroup. This results in incorrect
 			 * patch IDs when instanced draws are used.
 			 *
 			 * The intended solution is to restrict threadgroups to
 			 * a single instance by setting SWITCH_ON_EOI, which
-- 
2.9.3