[Mesa-dev] [PATCH] i965: Move MOCS macros to brw_state.h.

[Pohjolainen, Topi]

On Thu, May 04, 2017 at 11:49:08AM -0700, Rafael Antognolli wrote:
> brw_state.h is a better place to keep them, instead of brw_context.h.

Thanks for the follow-up :)

> 
> Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_context.h | 42 ---------------------------------
>  src/mesa/drivers/dri/i965/brw_state.h   | 42 +++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 42 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> index df7b6eb..723c5d6 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -397,48 +397,6 @@ struct brw_cache {
>     bool bo_used_by_gpu;
>  };
>  
> -/* Memory Object Control State:
> - * Specifying zero for L3 means "uncached in L3", at least on Haswell
> - * and Baytrail, since there are no PTE flags for setting L3 cacheability.
> - * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
> - * may still respect that.
> - */
> -#define GEN7_MOCS_L3                    1
> -
> -/* Ivybridge only: cache in LLC.
> - * Specifying zero here means to use the PTE values set by the kernel;
> - * non-zero overrides the PTE values.
> - */
> -#define IVB_MOCS_LLC                    (1 << 1)
> -
> -/* Baytrail only: snoop in CPU cache */
> -#define BYT_MOCS_SNOOP                  (1 << 1)
> -
> -/* Haswell only: LLC/eLLC controls (write-back or uncached).
> - * Specifying zero here means to use the PTE values set by the kernel,
> - * which is useful since it offers additional control (write-through
> - * cacheing and age).  Non-zero overrides the PTE values.
> - */
> -#define HSW_MOCS_UC_LLC_UC_ELLC         (1 << 1)
> -#define HSW_MOCS_WB_LLC_WB_ELLC         (2 << 1)
> -#define HSW_MOCS_UC_LLC_WB_ELLC         (3 << 1)
> -
> -/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
> - * and let you force write-back (WB) or write-through (WT) caching, or leave
> - * it up to the page table entry (PTE) specified by the kernel.
> - */
> -#define BDW_MOCS_WB  0x78
> -#define BDW_MOCS_WT  0x58
> -#define BDW_MOCS_PTE 0x18
> -
> -/* Skylake: MOCS is now an index into an array of 62 different caching
> - * configurations programmed by the kernel.
> - */
> -/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
> -#define SKL_MOCS_WB  (2 << 1)
> -/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
> -#define SKL_MOCS_PTE (1 << 1)
> -
>  /* Considered adding a member to this struct to document which flags
>   * an update might raise so that ordering of the state atoms can be
>   * checked or derived at runtime.  Dropped the idea in favor of having
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
> index d2d3d7c..5b51dc0 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -368,6 +368,48 @@ void gen9_init_atoms(struct brw_context *brw);
>  
>  void upload_gs_state_for_tf(struct brw_context *brw);
>  
> +/* Memory Object Control State:
> + * Specifying zero for L3 means "uncached in L3", at least on Haswell
> + * and Baytrail, since there are no PTE flags for setting L3 cacheability.
> + * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
> + * may still respect that.
> + */
> +#define GEN7_MOCS_L3                    1
> +
> +/* Ivybridge only: cache in LLC.
> + * Specifying zero here means to use the PTE values set by the kernel;
> + * non-zero overrides the PTE values.
> + */
> +#define IVB_MOCS_LLC                    (1 << 1)
> +
> +/* Baytrail only: snoop in CPU cache */
> +#define BYT_MOCS_SNOOP                  (1 << 1)
> +
> +/* Haswell only: LLC/eLLC controls (write-back or uncached).
> + * Specifying zero here means to use the PTE values set by the kernel,
> + * which is useful since it offers additional control (write-through
> + * cacheing and age).  Non-zero overrides the PTE values.
> + */
> +#define HSW_MOCS_UC_LLC_UC_ELLC         (1 << 1)
> +#define HSW_MOCS_WB_LLC_WB_ELLC         (2 << 1)
> +#define HSW_MOCS_UC_LLC_WB_ELLC         (3 << 1)
> +
> +/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
> + * and let you force write-back (WB) or write-through (WT) caching, or leave
> + * it up to the page table entry (PTE) specified by the kernel.
> + */
> +#define BDW_MOCS_WB  0x78
> +#define BDW_MOCS_WT  0x58
> +#define BDW_MOCS_PTE 0x18
> +
> +/* Skylake: MOCS is now an index into an array of 62 different caching
> + * configurations programmed by the kernel.
> + */
> +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
> +#define SKL_MOCS_WB  (2 << 1)
> +/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
> +#define SKL_MOCS_PTE (1 << 1)
> +
>  #ifdef __cplusplus
>  }
>  #endif
> -- 
> 2.9.3
> 
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