[Mesa-dev] [PATCH v2 2/2] anv/i965: drop libdrm_intel dependency completely
Daniel Vetter
daniel at ffwll.ch
Fri May 5 14:36:52 UTC 2017
On Thu, May 04, 2017 at 12:19:22PM -0700, Lionel Landwerlin wrote:
> With Ken's work to drop the library dependency on libdrm_intel, we now
> only depend on libdrm_intel for the kernel uapi headers it provides.
> It seems like we're better off just embeddeding those headers
> ourselves, making the lives of people developing news features tightly
> integrated with the kernel a tiny bit easier.
>
> v2: Just drop libdrm_intel, not libdrm (Lionel)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Header files need to be generated by the make headers_install target in
the kernel, and then the resulting stuff imported (it lands in
kernel-src/usr/include/drm/).
Otherwise you end up with kernel #defines gunk in userspace, which sooner
or later will clash with glibc and other fun. I also recommend you
reference the exact kernel sha1 or release you've used to generate these.
-Daniel
> ---
> configure.ac | 4 +-
> src/intel/Makefile.drm.am | 22 +
> src/intel/Makefile.sources | 4 +
> src/intel/Makefile.vulkan.am | 3 +-
> src/intel/drm/drm.h | 907 +++++++++++++++++++++
> src/intel/drm/drm_fourcc.h | 313 +++++++
> src/intel/drm/drm_mode.h | 692 ++++++++++++++++
> src/intel/drm/i915_drm.h | 1446 +++++++++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/Makefile.am | 3 +-
> 9 files changed, 3390 insertions(+), 4 deletions(-)
> create mode 100644 src/intel/Makefile.drm.am
> create mode 100644 src/intel/drm/drm.h
> create mode 100644 src/intel/drm/drm_fourcc.h
> create mode 100644 src/intel/drm/drm_mode.h
> create mode 100644 src/intel/drm/i915_drm.h
>
> diff --git a/configure.ac b/configure.ac
> index ba042791ad1..c90947f4922 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1745,7 +1745,7 @@ if test -n "$with_dri_drivers"; then
> xi965)
> require_libdrm "i965"
> HAVE_I965_DRI=yes
> - PKG_CHECK_MODULES([INTEL], [libdrm >= $LIBDRM_INTEL_REQUIRED libdrm_intel >= $LIBDRM_INTEL_REQUIRED])
> + PKG_CHECK_MODULES([INTEL], [libdrm >= $LIBDRM_INTEL_REQUIRED])
> ;;
> xnouveau)
> require_libdrm "nouveau"
> @@ -1849,7 +1849,7 @@ if test -n "$with_vulkan_drivers"; then
> case "x$driver" in
> xintel)
> require_libdrm "ANV"
> - PKG_CHECK_MODULES([INTEL], [libdrm >= $LIBDRM_INTEL_REQUIRED libdrm_intel >= $LIBDRM_INTEL_REQUIRED])
> + PKG_CHECK_MODULES([INTEL], [libdrm >= $LIBDRM_INTEL_REQUIRED])
> HAVE_INTEL_VULKAN=yes
> ;;
> xradeon)
> diff --git a/src/intel/Makefile.drm.am b/src/intel/Makefile.drm.am
> new file mode 100644
> index 00000000000..af4e4afbcde
> --- /dev/null
> +++ b/src/intel/Makefile.drm.am
> @@ -0,0 +1,22 @@
> +# Copyright 2017 Intel Corporation
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice (including the next
> +# paragraph) shall be included in all copies or substantial portions of the
> +# Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> +# IN THE SOFTWARE.
> +
> +EXTRA_DIST += $(DRM_INTEL_FILES)
> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> index 83200c3d7d8..2b12c96eb9e 100644
> --- a/src/intel/Makefile.sources
> +++ b/src/intel/Makefile.sources
> @@ -109,6 +109,10 @@ COMPILER_FILES = \
> COMPILER_GENERATED_FILES = \
> compiler/brw_nir_trig_workarounds.c
>
> +DRM_INTEL_FILES = \
> + drm/drm.h \
> + drm/i915_drm.h
> +
> GENXML_XML_FILES = \
> genxml/gen4.xml \
> genxml/gen45.xml \
> diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
> index ba6ab4fc93f..740b6da5413 100644
> --- a/src/intel/Makefile.vulkan.am
> +++ b/src/intel/Makefile.vulkan.am
> @@ -83,13 +83,14 @@ VULKAN_CFLAGS = \
> VULKAN_CPPFLAGS = \
> -I$(top_srcdir)/src/compiler \
> -I$(top_srcdir)/src/intel/compiler \
> + -I$(top_srcdir)/src/intel/drm \
> -I$(top_builddir)/src/intel/vulkan \
> -I$(top_srcdir)/src/intel/vulkan \
> -I$(top_srcdir)/src/vulkan/wsi \
> -I$(top_builddir)/src/vulkan/util \
> -I$(top_srcdir)/src/vulkan/util \
> $(AM_CPPFLAGS) \
> - $(LIBDRM_CFLAGS)
> + -D__user=
>
> vulkan_libanv_gen7_la_CFLAGS = $(VULKAN_CFLAGS)
> vulkan_libanv_gen7_la_CPPFLAGS = $(VULKAN_CPPFLAGS) -DGEN_VERSIONx10=70
> diff --git a/src/intel/drm/drm.h b/src/intel/drm/drm.h
> new file mode 100644
> index 00000000000..42d9f64ce41
> --- /dev/null
> +++ b/src/intel/drm/drm.h
> @@ -0,0 +1,907 @@
> +/**
> + * \file drm.h
> + * Header for the Direct Rendering Manager
> + *
> + * \author Rickard E. (Rik) Faith <faith at valinux.com>
> + *
> + * \par Acknowledgments:
> + * Dec 1999, Richard Henderson <rth at twiddle.net>, move to generic \c cmpxchg.
> + */
> +
> +/*
> + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
> + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
> + * All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef _DRM_H_
> +#define _DRM_H_
> +
> +#if defined(__KERNEL__)
> +
> +#include <linux/types.h>
> +#include <asm/ioctl.h>
> +typedef unsigned int drm_handle_t;
> +
> +#elif defined(__linux__)
> +
> +#include <linux/types.h>
> +#include <asm/ioctl.h>
> +typedef unsigned int drm_handle_t;
> +
> +#else /* One of the BSDs */
> +
> +#include <sys/ioccom.h>
> +#include <sys/types.h>
> +typedef int8_t __s8;
> +typedef uint8_t __u8;
> +typedef int16_t __s16;
> +typedef uint16_t __u16;
> +typedef int32_t __s32;
> +typedef uint32_t __u32;
> +typedef int64_t __s64;
> +typedef uint64_t __u64;
> +typedef size_t __kernel_size_t;
> +typedef unsigned long drm_handle_t;
> +
> +#endif
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
> +#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
> +#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
> +#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
> +
> +#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
> +#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
> +#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
> +#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
> +#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
> +
> +typedef unsigned int drm_context_t;
> +typedef unsigned int drm_drawable_t;
> +typedef unsigned int drm_magic_t;
> +
> +/**
> + * Cliprect.
> + *
> + * \warning: If you change this structure, make sure you change
> + * XF86DRIClipRectRec in the server as well
> + *
> + * \note KW: Actually it's illegal to change either for
> + * backwards-compatibility reasons.
> + */
> +struct drm_clip_rect {
> + unsigned short x1;
> + unsigned short y1;
> + unsigned short x2;
> + unsigned short y2;
> +};
> +
> +/**
> + * Drawable information.
> + */
> +struct drm_drawable_info {
> + unsigned int num_rects;
> + struct drm_clip_rect *rects;
> +};
> +
> +/**
> + * Texture region,
> + */
> +struct drm_tex_region {
> + unsigned char next;
> + unsigned char prev;
> + unsigned char in_use;
> + unsigned char padding;
> + unsigned int age;
> +};
> +
> +/**
> + * Hardware lock.
> + *
> + * The lock structure is a simple cache-line aligned integer. To avoid
> + * processor bus contention on a multiprocessor system, there should not be any
> + * other data stored in the same cache line.
> + */
> +struct drm_hw_lock {
> + __volatile__ unsigned int lock; /**< lock variable */
> + char padding[60]; /**< Pad to cache line */
> +};
> +
> +/**
> + * DRM_IOCTL_VERSION ioctl argument type.
> + *
> + * \sa drmGetVersion().
> + */
> +struct drm_version {
> + int version_major; /**< Major version */
> + int version_minor; /**< Minor version */
> + int version_patchlevel; /**< Patch level */
> + __kernel_size_t name_len; /**< Length of name buffer */
> + char __user *name; /**< Name of driver */
> + __kernel_size_t date_len; /**< Length of date buffer */
> + char __user *date; /**< User-space buffer to hold date */
> + __kernel_size_t desc_len; /**< Length of desc buffer */
> + char __user *desc; /**< User-space buffer to hold desc */
> +};
> +
> +/**
> + * DRM_IOCTL_GET_UNIQUE ioctl argument type.
> + *
> + * \sa drmGetBusid() and drmSetBusId().
> + */
> +struct drm_unique {
> + __kernel_size_t unique_len; /**< Length of unique */
> + char __user *unique; /**< Unique name for driver instantiation */
> +};
> +
> +struct drm_list {
> + int count; /**< Length of user-space structures */
> + struct drm_version __user *version;
> +};
> +
> +struct drm_block {
> + int unused;
> +};
> +
> +/**
> + * DRM_IOCTL_CONTROL ioctl argument type.
> + *
> + * \sa drmCtlInstHandler() and drmCtlUninstHandler().
> + */
> +struct drm_control {
> + enum {
> + DRM_ADD_COMMAND,
> + DRM_RM_COMMAND,
> + DRM_INST_HANDLER,
> + DRM_UNINST_HANDLER
> + } func;
> + int irq;
> +};
> +
> +/**
> + * Type of memory to map.
> + */
> +enum drm_map_type {
> + _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
> + _DRM_REGISTERS = 1, /**< no caching, no core dump */
> + _DRM_SHM = 2, /**< shared, cached */
> + _DRM_AGP = 3, /**< AGP/GART */
> + _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
> + _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
> +};
> +
> +/**
> + * Memory mapping flags.
> + */
> +enum drm_map_flags {
> + _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
> + _DRM_READ_ONLY = 0x02,
> + _DRM_LOCKED = 0x04, /**< shared, cached, locked */
> + _DRM_KERNEL = 0x08, /**< kernel requires access */
> + _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
> + _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
> + _DRM_REMOVABLE = 0x40, /**< Removable mapping */
> + _DRM_DRIVER = 0x80 /**< Managed by driver */
> +};
> +
> +struct drm_ctx_priv_map {
> + unsigned int ctx_id; /**< Context requesting private mapping */
> + void *handle; /**< Handle of map */
> +};
> +
> +/**
> + * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
> + * argument type.
> + *
> + * \sa drmAddMap().
> + */
> +struct drm_map {
> + unsigned long offset; /**< Requested physical address (0 for SAREA)*/
> + unsigned long size; /**< Requested physical size (bytes) */
> + enum drm_map_type type; /**< Type of memory to map */
> + enum drm_map_flags flags; /**< Flags */
> + void *handle; /**< User-space: "Handle" to pass to mmap() */
> + /**< Kernel-space: kernel-virtual address */
> + int mtrr; /**< MTRR slot used */
> + /* Private data */
> +};
> +
> +/**
> + * DRM_IOCTL_GET_CLIENT ioctl argument type.
> + */
> +struct drm_client {
> + int idx; /**< Which client desired? */
> + int auth; /**< Is client authenticated? */
> + unsigned long pid; /**< Process ID */
> + unsigned long uid; /**< User ID */
> + unsigned long magic; /**< Magic */
> + unsigned long iocs; /**< Ioctl count */
> +};
> +
> +enum drm_stat_type {
> + _DRM_STAT_LOCK,
> + _DRM_STAT_OPENS,
> + _DRM_STAT_CLOSES,
> + _DRM_STAT_IOCTLS,
> + _DRM_STAT_LOCKS,
> + _DRM_STAT_UNLOCKS,
> + _DRM_STAT_VALUE, /**< Generic value */
> + _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
> + _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
> +
> + _DRM_STAT_IRQ, /**< IRQ */
> + _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
> + _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
> + _DRM_STAT_DMA, /**< DMA */
> + _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
> + _DRM_STAT_MISSED /**< Missed DMA opportunity */
> + /* Add to the *END* of the list */
> +};
> +
> +/**
> + * DRM_IOCTL_GET_STATS ioctl argument type.
> + */
> +struct drm_stats {
> + unsigned long count;
> + struct {
> + unsigned long value;
> + enum drm_stat_type type;
> + } data[15];
> +};
> +
> +/**
> + * Hardware locking flags.
> + */
> +enum drm_lock_flags {
> + _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
> + _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
> + _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
> + _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
> + /* These *HALT* flags aren't supported yet
> + -- they will be used to support the
> + full-screen DGA-like mode. */
> + _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
> + _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
> +};
> +
> +/**
> + * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
> + *
> + * \sa drmGetLock() and drmUnlock().
> + */
> +struct drm_lock {
> + int context;
> + enum drm_lock_flags flags;
> +};
> +
> +/**
> + * DMA flags
> + *
> + * \warning
> + * These values \e must match xf86drm.h.
> + *
> + * \sa drm_dma.
> + */
> +enum drm_dma_flags {
> + /* Flags for DMA buffer dispatch */
> + _DRM_DMA_BLOCK = 0x01, /**<
> + * Block until buffer dispatched.
> + *
> + * \note The buffer may not yet have
> + * been processed by the hardware --
> + * getting a hardware lock with the
> + * hardware quiescent will ensure
> + * that the buffer has been
> + * processed.
> + */
> + _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
> + _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
> +
> + /* Flags for DMA buffer request */
> + _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
> + _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
> + _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
> +};
> +
> +/**
> + * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
> + *
> + * \sa drmAddBufs().
> + */
> +struct drm_buf_desc {
> + int count; /**< Number of buffers of this size */
> + int size; /**< Size in bytes */
> + int low_mark; /**< Low water mark */
> + int high_mark; /**< High water mark */
> + enum {
> + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
> + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
> + _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
> + _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
> + _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
> + } flags;
> + unsigned long agp_start; /**<
> + * Start address of where the AGP buffers are
> + * in the AGP aperture
> + */
> +};
> +
> +/**
> + * DRM_IOCTL_INFO_BUFS ioctl argument type.
> + */
> +struct drm_buf_info {
> + int count; /**< Entries in list */
> + struct drm_buf_desc __user *list;
> +};
> +
> +/**
> + * DRM_IOCTL_FREE_BUFS ioctl argument type.
> + */
> +struct drm_buf_free {
> + int count;
> + int __user *list;
> +};
> +
> +/**
> + * Buffer information
> + *
> + * \sa drm_buf_map.
> + */
> +struct drm_buf_pub {
> + int idx; /**< Index into the master buffer list */
> + int total; /**< Buffer size */
> + int used; /**< Amount of buffer in use (for DMA) */
> + void __user *address; /**< Address of buffer */
> +};
> +
> +/**
> + * DRM_IOCTL_MAP_BUFS ioctl argument type.
> + */
> +struct drm_buf_map {
> + int count; /**< Length of the buffer list */
> +#ifdef __cplusplus
> + void __user *virt;
> +#else
> + void __user *virtual; /**< Mmap'd area in user-virtual */
> +#endif
> + struct drm_buf_pub __user *list; /**< Buffer information */
> +};
> +
> +/**
> + * DRM_IOCTL_DMA ioctl argument type.
> + *
> + * Indices here refer to the offset into the buffer list in drm_buf_get.
> + *
> + * \sa drmDMA().
> + */
> +struct drm_dma {
> + int context; /**< Context handle */
> + int send_count; /**< Number of buffers to send */
> + int __user *send_indices; /**< List of handles to buffers */
> + int __user *send_sizes; /**< Lengths of data to send */
> + enum drm_dma_flags flags; /**< Flags */
> + int request_count; /**< Number of buffers requested */
> + int request_size; /**< Desired size for buffers */
> + int __user *request_indices; /**< Buffer information */
> + int __user *request_sizes;
> + int granted_count; /**< Number of buffers granted */
> +};
> +
> +enum drm_ctx_flags {
> + _DRM_CONTEXT_PRESERVED = 0x01,
> + _DRM_CONTEXT_2DONLY = 0x02
> +};
> +
> +/**
> + * DRM_IOCTL_ADD_CTX ioctl argument type.
> + *
> + * \sa drmCreateContext() and drmDestroyContext().
> + */
> +struct drm_ctx {
> + drm_context_t handle;
> + enum drm_ctx_flags flags;
> +};
> +
> +/**
> + * DRM_IOCTL_RES_CTX ioctl argument type.
> + */
> +struct drm_ctx_res {
> + int count;
> + struct drm_ctx __user *contexts;
> +};
> +
> +/**
> + * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
> + */
> +struct drm_draw {
> + drm_drawable_t handle;
> +};
> +
> +/**
> + * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
> + */
> +typedef enum {
> + DRM_DRAWABLE_CLIPRECTS
> +} drm_drawable_info_type_t;
> +
> +struct drm_update_draw {
> + drm_drawable_t handle;
> + unsigned int type;
> + unsigned int num;
> + unsigned long long data;
> +};
> +
> +/**
> + * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
> + */
> +struct drm_auth {
> + drm_magic_t magic;
> +};
> +
> +/**
> + * DRM_IOCTL_IRQ_BUSID ioctl argument type.
> + *
> + * \sa drmGetInterruptFromBusID().
> + */
> +struct drm_irq_busid {
> + int irq; /**< IRQ number */
> + int busnum; /**< bus number */
> + int devnum; /**< device number */
> + int funcnum; /**< function number */
> +};
> +
> +enum drm_vblank_seq_type {
> + _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
> + _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
> + /* bits 1-6 are reserved for high crtcs */
> + _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
> + _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
> + _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
> + _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
> + _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
> + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
> +};
> +#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
> +
> +#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
> +#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
> + _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
> +
> +struct drm_wait_vblank_request {
> + enum drm_vblank_seq_type type;
> + unsigned int sequence;
> + unsigned long signal;
> +};
> +
> +struct drm_wait_vblank_reply {
> + enum drm_vblank_seq_type type;
> + unsigned int sequence;
> + long tval_sec;
> + long tval_usec;
> +};
> +
> +/**
> + * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
> + *
> + * \sa drmWaitVBlank().
> + */
> +union drm_wait_vblank {
> + struct drm_wait_vblank_request request;
> + struct drm_wait_vblank_reply reply;
> +};
> +
> +#define _DRM_PRE_MODESET 1
> +#define _DRM_POST_MODESET 2
> +
> +/**
> + * DRM_IOCTL_MODESET_CTL ioctl argument type
> + *
> + * \sa drmModesetCtl().
> + */
> +struct drm_modeset_ctl {
> + __u32 crtc;
> + __u32 cmd;
> +};
> +
> +/**
> + * DRM_IOCTL_AGP_ENABLE ioctl argument type.
> + *
> + * \sa drmAgpEnable().
> + */
> +struct drm_agp_mode {
> + unsigned long mode; /**< AGP mode */
> +};
> +
> +/**
> + * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
> + *
> + * \sa drmAgpAlloc() and drmAgpFree().
> + */
> +struct drm_agp_buffer {
> + unsigned long size; /**< In bytes -- will round to page boundary */
> + unsigned long handle; /**< Used for binding / unbinding */
> + unsigned long type; /**< Type of memory to allocate */
> + unsigned long physical; /**< Physical used by i810 */
> +};
> +
> +/**
> + * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
> + *
> + * \sa drmAgpBind() and drmAgpUnbind().
> + */
> +struct drm_agp_binding {
> + unsigned long handle; /**< From drm_agp_buffer */
> + unsigned long offset; /**< In bytes -- will round to page boundary */
> +};
> +
> +/**
> + * DRM_IOCTL_AGP_INFO ioctl argument type.
> + *
> + * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
> + * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
> + * drmAgpVendorId() and drmAgpDeviceId().
> + */
> +struct drm_agp_info {
> + int agp_version_major;
> + int agp_version_minor;
> + unsigned long mode;
> + unsigned long aperture_base; /* physical address */
> + unsigned long aperture_size; /* bytes */
> + unsigned long memory_allowed; /* bytes */
> + unsigned long memory_used;
> +
> + /* PCI information */
> + unsigned short id_vendor;
> + unsigned short id_device;
> +};
> +
> +/**
> + * DRM_IOCTL_SG_ALLOC ioctl argument type.
> + */
> +struct drm_scatter_gather {
> + unsigned long size; /**< In bytes -- will round to page boundary */
> + unsigned long handle; /**< Used for mapping / unmapping */
> +};
> +
> +/**
> + * DRM_IOCTL_SET_VERSION ioctl argument type.
> + */
> +struct drm_set_version {
> + int drm_di_major;
> + int drm_di_minor;
> + int drm_dd_major;
> + int drm_dd_minor;
> +};
> +
> +/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
> +struct drm_gem_close {
> + /** Handle of the object to be closed. */
> + __u32 handle;
> + __u32 pad;
> +};
> +
> +/** DRM_IOCTL_GEM_FLINK ioctl argument type */
> +struct drm_gem_flink {
> + /** Handle for the object being named */
> + __u32 handle;
> +
> + /** Returned global name */
> + __u32 name;
> +};
> +
> +/** DRM_IOCTL_GEM_OPEN ioctl argument type */
> +struct drm_gem_open {
> + /** Name of object being opened */
> + __u32 name;
> +
> + /** Returned handle for the object */
> + __u32 handle;
> +
> + /** Returned size of the object */
> + __u64 size;
> +};
> +
> +#define DRM_CAP_DUMB_BUFFER 0x1
> +#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
> +#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
> +#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
> +#define DRM_CAP_PRIME 0x5
> +#define DRM_PRIME_CAP_IMPORT 0x1
> +#define DRM_PRIME_CAP_EXPORT 0x2
> +#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
> +#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
> +/*
> + * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
> + * combination for the hardware cursor. The intention is that a hardware
> + * agnostic userspace can query a cursor plane size to use.
> + *
> + * Note that the cross-driver contract is to merely return a valid size;
> + * drivers are free to attach another meaning on top, eg. i915 returns the
> + * maximum plane size.
> + */
> +#define DRM_CAP_CURSOR_WIDTH 0x8
> +#define DRM_CAP_CURSOR_HEIGHT 0x9
> +#define DRM_CAP_ADDFB2_MODIFIERS 0x10
> +#define DRM_CAP_PAGE_FLIP_TARGET 0x11
> +#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
> +
> +/** DRM_IOCTL_GET_CAP ioctl argument type */
> +struct drm_get_cap {
> + __u64 capability;
> + __u64 value;
> +};
> +
> +/**
> + * DRM_CLIENT_CAP_STEREO_3D
> + *
> + * if set to 1, the DRM core will expose the stereo 3D capabilities of the
> + * monitor by advertising the supported 3D layouts in the flags of struct
> + * drm_mode_modeinfo.
> + */
> +#define DRM_CLIENT_CAP_STEREO_3D 1
> +
> +/**
> + * DRM_CLIENT_CAP_UNIVERSAL_PLANES
> + *
> + * If set to 1, the DRM core will expose all planes (overlay, primary, and
> + * cursor) to userspace.
> + */
> +#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
> +
> +/**
> + * DRM_CLIENT_CAP_ATOMIC
> + *
> + * If set to 1, the DRM core will expose atomic properties to userspace
> + */
> +#define DRM_CLIENT_CAP_ATOMIC 3
> +
> +/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
> +struct drm_set_client_cap {
> + __u64 capability;
> + __u64 value;
> +};
> +
> +#define DRM_RDWR O_RDWR
> +#define DRM_CLOEXEC O_CLOEXEC
> +struct drm_prime_handle {
> + __u32 handle;
> +
> + /** Flags.. only applicable for handle->fd */
> + __u32 flags;
> +
> + /** Returned dmabuf file descriptor */
> + __s32 fd;
> +};
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#include "drm_mode.h"
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +#define DRM_IOCTL_BASE 'd'
> +#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
> +#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
> +#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
> +#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
> +
> +#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
> +#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
> +#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
> +#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
> +#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
> +#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
> +#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
> +#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
> +#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
> +#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
> +#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
> +#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
> +#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
> +#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
> +
> +#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
> +#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
> +#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
> +#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
> +#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
> +#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
> +#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
> +#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
> +#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
> +#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
> +#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
> +
> +#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
> +
> +#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
> +#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
> +
> +#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
> +#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
> +
> +#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
> +#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
> +#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
> +#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
> +#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
> +#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
> +#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
> +#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
> +#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
> +#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
> +#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
> +#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
> +#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
> +
> +#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
> +#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
> +
> +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
> +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
> +#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
> +#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
> +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
> +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
> +#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
> +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
> +
> +#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
> +#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
> +
> +#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
> +
> +#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
> +
> +#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
> +#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
> +#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
> +#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
> +#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
> +#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
> +#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
> +#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
> +#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
> +#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
> +
> +#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
> +#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
> +#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
> +#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
> +#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
> +#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
> +#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
> +#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
> +
> +#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
> +#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
> +#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
> +#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
> +#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
> +#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
> +#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
> +#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
> +#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
> +#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
> +#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
> +#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
> +#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
> +
> +/**
> + * Device specific ioctls should only be in their respective headers
> + * The device specific ioctl range is from 0x40 to 0x9f.
> + * Generic IOCTLS restart at 0xA0.
> + *
> + * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
> + * drmCommandReadWrite().
> + */
> +#define DRM_COMMAND_BASE 0x40
> +#define DRM_COMMAND_END 0xA0
> +
> +/**
> + * Header for events written back to userspace on the drm fd. The
> + * type defines the type of event, the length specifies the total
> + * length of the event (including the header), and user_data is
> + * typically a 64 bit value passed with the ioctl that triggered the
> + * event. A read on the drm fd will always only return complete
> + * events, that is, if for example the read buffer is 100 bytes, and
> + * there are two 64 byte events pending, only one will be returned.
> + *
> + * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
> + * up are chipset specific.
> + */
> +struct drm_event {
> + __u32 type;
> + __u32 length;
> +};
> +
> +#define DRM_EVENT_VBLANK 0x01
> +#define DRM_EVENT_FLIP_COMPLETE 0x02
> +
> +struct drm_event_vblank {
> + struct drm_event base;
> + __u64 user_data;
> + __u32 tv_sec;
> + __u32 tv_usec;
> + __u32 sequence;
> + __u32 crtc_id; /* 0 on older kernels that do not support this */
> +};
> +
> +/* typedef area */
> +#ifndef __KERNEL__
> +typedef struct drm_clip_rect drm_clip_rect_t;
> +typedef struct drm_drawable_info drm_drawable_info_t;
> +typedef struct drm_tex_region drm_tex_region_t;
> +typedef struct drm_hw_lock drm_hw_lock_t;
> +typedef struct drm_version drm_version_t;
> +typedef struct drm_unique drm_unique_t;
> +typedef struct drm_list drm_list_t;
> +typedef struct drm_block drm_block_t;
> +typedef struct drm_control drm_control_t;
> +typedef enum drm_map_type drm_map_type_t;
> +typedef enum drm_map_flags drm_map_flags_t;
> +typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
> +typedef struct drm_map drm_map_t;
> +typedef struct drm_client drm_client_t;
> +typedef enum drm_stat_type drm_stat_type_t;
> +typedef struct drm_stats drm_stats_t;
> +typedef enum drm_lock_flags drm_lock_flags_t;
> +typedef struct drm_lock drm_lock_t;
> +typedef enum drm_dma_flags drm_dma_flags_t;
> +typedef struct drm_buf_desc drm_buf_desc_t;
> +typedef struct drm_buf_info drm_buf_info_t;
> +typedef struct drm_buf_free drm_buf_free_t;
> +typedef struct drm_buf_pub drm_buf_pub_t;
> +typedef struct drm_buf_map drm_buf_map_t;
> +typedef struct drm_dma drm_dma_t;
> +typedef union drm_wait_vblank drm_wait_vblank_t;
> +typedef struct drm_agp_mode drm_agp_mode_t;
> +typedef enum drm_ctx_flags drm_ctx_flags_t;
> +typedef struct drm_ctx drm_ctx_t;
> +typedef struct drm_ctx_res drm_ctx_res_t;
> +typedef struct drm_draw drm_draw_t;
> +typedef struct drm_update_draw drm_update_draw_t;
> +typedef struct drm_auth drm_auth_t;
> +typedef struct drm_irq_busid drm_irq_busid_t;
> +typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
> +
> +typedef struct drm_agp_buffer drm_agp_buffer_t;
> +typedef struct drm_agp_binding drm_agp_binding_t;
> +typedef struct drm_agp_info drm_agp_info_t;
> +typedef struct drm_scatter_gather drm_scatter_gather_t;
> +typedef struct drm_set_version drm_set_version_t;
> +#endif
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#endif
> diff --git a/src/intel/drm/drm_fourcc.h b/src/intel/drm/drm_fourcc.h
> new file mode 100644
> index 00000000000..995c8f9c692
> --- /dev/null
> +++ b/src/intel/drm/drm_fourcc.h
> @@ -0,0 +1,313 @@
> +/*
> + * Copyright 2011 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef DRM_FOURCC_H
> +#define DRM_FOURCC_H
> +
> +#include "drm.h"
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
> + ((__u32)(c) << 16) | ((__u32)(d) << 24))
> +
> +#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
> +
> +/* color index */
> +#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> +
> +/* 8 bpp Red */
> +#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> +
> +/* 16 bpp Red */
> +#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
> +
> +/* 16 bpp RG */
> +#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
> +#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
> +
> +/* 32 bpp RG */
> +#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
> +#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
> +
> +/* 8 bpp RGB */
> +#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
> +#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
> +
> +/* 16 bpp RGB */
> +#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
> +#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
> +#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
> +#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
> +
> +#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
> +#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
> +#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
> +#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
> +
> +#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
> +#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
> +#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
> +#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
> +
> +#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
> +#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
> +#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
> +#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
> +
> +#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
> +#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
> +
> +/* 24 bpp RGB */
> +#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
> +#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
> +
> +/* 32 bpp RGB */
> +#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
> +#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
> +#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
> +#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
> +
> +#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
> +#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
> +#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
> +#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
> +
> +#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
> +#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
> +#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
> +#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
> +
> +#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
> +#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
> +#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
> +#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
> +
> +/* packed YCbCr */
> +#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
> +#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
> +#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
> +#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
> +
> +#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +
> +/*
> + * 2 plane RGB + A
> + * index 0 = RGB plane, same format as the corresponding non _A8 format has
> + * index 1 = A plane, [7:0] A
> + */
> +#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
> +#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
> +#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
> +#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
> +#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
> +#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
> +#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
> +#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
> +
> +/*
> + * 2 plane YCbCr
> + * index 0 = Y plane, [7:0] Y
> + * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
> + * or
> + * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
> + */
> +#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
> +#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
> +#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> +
> +/*
> + * 3 plane YCbCr
> + * index 0: Y plane, [7:0] Y
> + * index 1: Cb plane, [7:0] Cb
> + * index 2: Cr plane, [7:0] Cr
> + * or
> + * index 1: Cr plane, [7:0] Cr
> + * index 2: Cb plane, [7:0] Cb
> + */
> +#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
> +#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
> +#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
> +#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
> +#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
> +#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
> +#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
> +#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
> +#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
> +#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
> +
> +
> +/*
> + * Format Modifiers:
> + *
> + * Format modifiers describe, typically, a re-ordering or modification
> + * of the data in a plane of an FB. This can be used to express tiled/
> + * swizzled formats, or compression, or a combination of the two.
> + *
> + * The upper 8 bits of the format modifier are a vendor-id as assigned
> + * below. The lower 56 bits are assigned as vendor sees fit.
> + */
> +
> +/* Vendor Ids: */
> +#define DRM_FORMAT_MOD_NONE 0
> +#define DRM_FORMAT_MOD_VENDOR_NONE 0
> +#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
> +#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
> +#define DRM_FORMAT_MOD_VENDOR_NV 0x03
> +#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
> +#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
> +#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
> +/* add more to the end as needed */
> +
> +#define fourcc_mod_code(vendor, val) \
> + ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
> +
> +/*
> + * Format Modifier tokens:
> + *
> + * When adding a new token please document the layout with a code comment,
> + * similar to the fourcc codes above. drm_fourcc.h is considered the
> + * authoritative source for all of these.
> + */
> +
> +/*
> + * Linear Layout
> + *
> + * Just plain linear layout. Note that this is different from no specifying any
> + * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
> + * which tells the driver to also take driver-internal information into account
> + * and so might actually result in a tiled framebuffer.
> + */
> +#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
> +
> +/* Intel framebuffer modifiers */
> +
> +/*
> + * Intel X-tiling layout
> + *
> + * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
> + * in row-major layout. Within the tile bytes are laid out row-major, with
> + * a platform-dependent stride. On top of that the memory can apply
> + * platform-depending swizzling of some higher address bits into bit6.
> + *
> + * This format is highly platforms specific and not useful for cross-driver
> + * sharing. It exists since on a given platform it does uniquely identify the
> + * layout in a simple way for i915-specific userspace.
> + */
> +#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
> +
> +/*
> + * Intel Y-tiling layout
> + *
> + * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
> + * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
> + * chunks column-major, with a platform-dependent height. On top of that the
> + * memory can apply platform-depending swizzling of some higher address bits
> + * into bit6.
> + *
> + * This format is highly platforms specific and not useful for cross-driver
> + * sharing. It exists since on a given platform it does uniquely identify the
> + * layout in a simple way for i915-specific userspace.
> + */
> +#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
> +
> +/*
> + * Intel Yf-tiling layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
> + * are arranged in four groups (two wide, two high) with column-major layout.
> + * Each group therefore consits out of four 256 byte units, which are also laid
> + * out as 2x2 column-major.
> + * 256 byte units are made out of four 64 byte blocks of pixels, producing
> + * either a square block or a 2:1 unit.
> + * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
> + * in pixel depends on the pixel depth.
> + */
> +#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
> +
> +/*
> + * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> + *
> + * Macroblocks are laid in a Z-shape, and each pixel data is following the
> + * standard NV12 style.
> + * As for NV12, an image is the result of two frame buffers: one for Y,
> + * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
> + * Alignment requirements are (for each buffer):
> + * - multiple of 128 pixels for the width
> + * - multiple of 32 pixels for the height
> + *
> + * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
> + */
> +#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
> +
> +/* Vivante framebuffer modifiers */
> +
> +/*
> + * Vivante 4x4 tiling layout
> + *
> + * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
> + * layout.
> + */
> +#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
> +
> +/*
> + * Vivante 64x64 super-tiling layout
> + *
> + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
> + * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
> + * major layout.
> + *
> + * For more information: see
> + * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
> + */
> +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
> +
> +/*
> + * Vivante 4x4 tiling layout for dual-pipe
> + *
> + * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
> + * different base address. Offsets from the base addresses are therefore halved
> + * compared to the non-split tiled layout.
> + */
> +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
> +
> +/*
> + * Vivante 64x64 super-tiling layout for dual-pipe
> + *
> + * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
> + * starts at a different base address. Offsets from the base addresses are
> + * therefore halved compared to the non-split super-tiled layout.
> + */
> +#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#endif /* DRM_FOURCC_H */
> diff --git a/src/intel/drm/drm_mode.h b/src/intel/drm/drm_mode.h
> new file mode 100644
> index 00000000000..8c67fc03d53
> --- /dev/null
> +++ b/src/intel/drm/drm_mode.h
> @@ -0,0 +1,692 @@
> +/*
> + * Copyright (c) 2007 Dave Airlie <airlied at linux.ie>
> + * Copyright (c) 2007 Jakob Bornecrantz <wallbraker at gmail.com>
> + * Copyright (c) 2008 Red Hat Inc.
> + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
> + * Copyright (c) 2007-2008 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef _DRM_MODE_H
> +#define _DRM_MODE_H
> +
> +#include "drm.h"
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +#define DRM_DISPLAY_INFO_LEN 32
> +#define DRM_CONNECTOR_NAME_LEN 32
> +#define DRM_DISPLAY_MODE_LEN 32
> +#define DRM_PROP_NAME_LEN 32
> +
> +#define DRM_MODE_TYPE_BUILTIN (1<<0)
> +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
> +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
> +#define DRM_MODE_TYPE_PREFERRED (1<<3)
> +#define DRM_MODE_TYPE_DEFAULT (1<<4)
> +#define DRM_MODE_TYPE_USERDEF (1<<5)
> +#define DRM_MODE_TYPE_DRIVER (1<<6)
> +
> +/* Video mode flags */
> +/* bit compatible with the xrandr RR_ definitions (bits 0-13)
> + *
> + * ABI warning: Existing userspace really expects
> + * the mode flags to match the xrandr definitions. Any
> + * changes that don't match the xrandr definitions will
> + * likely need a new client cap or some other mechanism
> + * to avoid breaking existing userspace. This includes
> + * allocating new flags in the previously unused bits!
> + */
> +#define DRM_MODE_FLAG_PHSYNC (1<<0)
> +#define DRM_MODE_FLAG_NHSYNC (1<<1)
> +#define DRM_MODE_FLAG_PVSYNC (1<<2)
> +#define DRM_MODE_FLAG_NVSYNC (1<<3)
> +#define DRM_MODE_FLAG_INTERLACE (1<<4)
> +#define DRM_MODE_FLAG_DBLSCAN (1<<5)
> +#define DRM_MODE_FLAG_CSYNC (1<<6)
> +#define DRM_MODE_FLAG_PCSYNC (1<<7)
> +#define DRM_MODE_FLAG_NCSYNC (1<<8)
> +#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
> +#define DRM_MODE_FLAG_BCAST (1<<10)
> +#define DRM_MODE_FLAG_PIXMUX (1<<11)
> +#define DRM_MODE_FLAG_DBLCLK (1<<12)
> +#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
> + /*
> + * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
> + * (define not exposed to user space).
> + */
> +#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
> +#define DRM_MODE_FLAG_3D_NONE (0<<14)
> +#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
> +#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
> +#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
> +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
> +#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
> +#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
> +#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
> +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
> +
> +/* Picture aspect ratio options */
> +#define DRM_MODE_PICTURE_ASPECT_NONE 0
> +#define DRM_MODE_PICTURE_ASPECT_4_3 1
> +#define DRM_MODE_PICTURE_ASPECT_16_9 2
> +
> +/* Aspect ratio flag bitmask (4 bits 22:19) */
> +#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
> +#define DRM_MODE_FLAG_PIC_AR_NONE \
> + (DRM_MODE_PICTURE_ASPECT_NONE<<19)
> +#define DRM_MODE_FLAG_PIC_AR_4_3 \
> + (DRM_MODE_PICTURE_ASPECT_4_3<<19)
> +#define DRM_MODE_FLAG_PIC_AR_16_9 \
> + (DRM_MODE_PICTURE_ASPECT_16_9<<19)
> +
> +/* DPMS flags */
> +/* bit compatible with the xorg definitions. */
> +#define DRM_MODE_DPMS_ON 0
> +#define DRM_MODE_DPMS_STANDBY 1
> +#define DRM_MODE_DPMS_SUSPEND 2
> +#define DRM_MODE_DPMS_OFF 3
> +
> +/* Scaling mode options */
> +#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
> + software can still scale) */
> +#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
> +#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
> +#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
> +
> +/* Dithering mode options */
> +#define DRM_MODE_DITHERING_OFF 0
> +#define DRM_MODE_DITHERING_ON 1
> +#define DRM_MODE_DITHERING_AUTO 2
> +
> +/* Dirty info options */
> +#define DRM_MODE_DIRTY_OFF 0
> +#define DRM_MODE_DIRTY_ON 1
> +#define DRM_MODE_DIRTY_ANNOTATE 2
> +
> +/* Link Status options */
> +#define DRM_MODE_LINK_STATUS_GOOD 0
> +#define DRM_MODE_LINK_STATUS_BAD 1
> +
> +struct drm_mode_modeinfo {
> + __u32 clock;
> + __u16 hdisplay;
> + __u16 hsync_start;
> + __u16 hsync_end;
> + __u16 htotal;
> + __u16 hskew;
> + __u16 vdisplay;
> + __u16 vsync_start;
> + __u16 vsync_end;
> + __u16 vtotal;
> + __u16 vscan;
> +
> + __u32 vrefresh;
> +
> + __u32 flags;
> + __u32 type;
> + char name[DRM_DISPLAY_MODE_LEN];
> +};
> +
> +struct drm_mode_card_res {
> + __u64 fb_id_ptr;
> + __u64 crtc_id_ptr;
> + __u64 connector_id_ptr;
> + __u64 encoder_id_ptr;
> + __u32 count_fbs;
> + __u32 count_crtcs;
> + __u32 count_connectors;
> + __u32 count_encoders;
> + __u32 min_width;
> + __u32 max_width;
> + __u32 min_height;
> + __u32 max_height;
> +};
> +
> +struct drm_mode_crtc {
> + __u64 set_connectors_ptr;
> + __u32 count_connectors;
> +
> + __u32 crtc_id; /**< Id */
> + __u32 fb_id; /**< Id of framebuffer */
> +
> + __u32 x; /**< x Position on the framebuffer */
> + __u32 y; /**< y Position on the framebuffer */
> +
> + __u32 gamma_size;
> + __u32 mode_valid;
> + struct drm_mode_modeinfo mode;
> +};
> +
> +#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
> +#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
> +
> +/* Planes blend with or override other bits on the CRTC */
> +struct drm_mode_set_plane {
> + __u32 plane_id;
> + __u32 crtc_id;
> + __u32 fb_id; /* fb object contains surface format type */
> + __u32 flags; /* see above flags */
> +
> + /* Signed dest location allows it to be partially off screen */
> + __s32 crtc_x;
> + __s32 crtc_y;
> + __u32 crtc_w;
> + __u32 crtc_h;
> +
> + /* Source values are 16.16 fixed point */
> + __u32 src_x;
> + __u32 src_y;
> + __u32 src_h;
> + __u32 src_w;
> +};
> +
> +struct drm_mode_get_plane {
> + __u32 plane_id;
> +
> + __u32 crtc_id;
> + __u32 fb_id;
> +
> + __u32 possible_crtcs;
> + __u32 gamma_size;
> +
> + __u32 count_format_types;
> + __u64 format_type_ptr;
> +};
> +
> +struct drm_mode_get_plane_res {
> + __u64 plane_id_ptr;
> + __u32 count_planes;
> +};
> +
> +#define DRM_MODE_ENCODER_NONE 0
> +#define DRM_MODE_ENCODER_DAC 1
> +#define DRM_MODE_ENCODER_TMDS 2
> +#define DRM_MODE_ENCODER_LVDS 3
> +#define DRM_MODE_ENCODER_TVDAC 4
> +#define DRM_MODE_ENCODER_VIRTUAL 5
> +#define DRM_MODE_ENCODER_DSI 6
> +#define DRM_MODE_ENCODER_DPMST 7
> +#define DRM_MODE_ENCODER_DPI 8
> +
> +struct drm_mode_get_encoder {
> + __u32 encoder_id;
> + __u32 encoder_type;
> +
> + __u32 crtc_id; /**< Id of crtc */
> +
> + __u32 possible_crtcs;
> + __u32 possible_clones;
> +};
> +
> +/* This is for connectors with multiple signal types. */
> +/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
> +enum drm_mode_subconnector {
> + DRM_MODE_SUBCONNECTOR_Automatic = 0,
> + DRM_MODE_SUBCONNECTOR_Unknown = 0,
> + DRM_MODE_SUBCONNECTOR_DVID = 3,
> + DRM_MODE_SUBCONNECTOR_DVIA = 4,
> + DRM_MODE_SUBCONNECTOR_Composite = 5,
> + DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
> + DRM_MODE_SUBCONNECTOR_Component = 8,
> + DRM_MODE_SUBCONNECTOR_SCART = 9,
> +};
> +
> +#define DRM_MODE_CONNECTOR_Unknown 0
> +#define DRM_MODE_CONNECTOR_VGA 1
> +#define DRM_MODE_CONNECTOR_DVII 2
> +#define DRM_MODE_CONNECTOR_DVID 3
> +#define DRM_MODE_CONNECTOR_DVIA 4
> +#define DRM_MODE_CONNECTOR_Composite 5
> +#define DRM_MODE_CONNECTOR_SVIDEO 6
> +#define DRM_MODE_CONNECTOR_LVDS 7
> +#define DRM_MODE_CONNECTOR_Component 8
> +#define DRM_MODE_CONNECTOR_9PinDIN 9
> +#define DRM_MODE_CONNECTOR_DisplayPort 10
> +#define DRM_MODE_CONNECTOR_HDMIA 11
> +#define DRM_MODE_CONNECTOR_HDMIB 12
> +#define DRM_MODE_CONNECTOR_TV 13
> +#define DRM_MODE_CONNECTOR_eDP 14
> +#define DRM_MODE_CONNECTOR_VIRTUAL 15
> +#define DRM_MODE_CONNECTOR_DSI 16
> +#define DRM_MODE_CONNECTOR_DPI 17
> +
> +struct drm_mode_get_connector {
> +
> + __u64 encoders_ptr;
> + __u64 modes_ptr;
> + __u64 props_ptr;
> + __u64 prop_values_ptr;
> +
> + __u32 count_modes;
> + __u32 count_props;
> + __u32 count_encoders;
> +
> + __u32 encoder_id; /**< Current Encoder */
> + __u32 connector_id; /**< Id */
> + __u32 connector_type;
> + __u32 connector_type_id;
> +
> + __u32 connection;
> + __u32 mm_width; /**< width in millimeters */
> + __u32 mm_height; /**< height in millimeters */
> + __u32 subpixel;
> +
> + __u32 pad;
> +};
> +
> +#define DRM_MODE_PROP_PENDING (1<<0)
> +#define DRM_MODE_PROP_RANGE (1<<1)
> +#define DRM_MODE_PROP_IMMUTABLE (1<<2)
> +#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
> +#define DRM_MODE_PROP_BLOB (1<<4)
> +#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
> +
> +/* non-extended types: legacy bitmask, one bit per type: */
> +#define DRM_MODE_PROP_LEGACY_TYPE ( \
> + DRM_MODE_PROP_RANGE | \
> + DRM_MODE_PROP_ENUM | \
> + DRM_MODE_PROP_BLOB | \
> + DRM_MODE_PROP_BITMASK)
> +
> +/* extended-types: rather than continue to consume a bit per type,
> + * grab a chunk of the bits to use as integer type id.
> + */
> +#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
> +#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
> +#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
> +#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
> +
> +/* the PROP_ATOMIC flag is used to hide properties from userspace that
> + * is not aware of atomic properties. This is mostly to work around
> + * older userspace (DDX drivers) that read/write each prop they find,
> + * witout being aware that this could be triggering a lengthy modeset.
> + */
> +#define DRM_MODE_PROP_ATOMIC 0x80000000
> +
> +struct drm_mode_property_enum {
> + __u64 value;
> + char name[DRM_PROP_NAME_LEN];
> +};
> +
> +struct drm_mode_get_property {
> + __u64 values_ptr; /* values and blob lengths */
> + __u64 enum_blob_ptr; /* enum and blob id ptrs */
> +
> + __u32 prop_id;
> + __u32 flags;
> + char name[DRM_PROP_NAME_LEN];
> +
> + __u32 count_values;
> + /* This is only used to count enum values, not blobs. The _blobs is
> + * simply because of a historical reason, i.e. backwards compat. */
> + __u32 count_enum_blobs;
> +};
> +
> +struct drm_mode_connector_set_property {
> + __u64 value;
> + __u32 prop_id;
> + __u32 connector_id;
> +};
> +
> +#define DRM_MODE_OBJECT_CRTC 0xcccccccc
> +#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
> +#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
> +#define DRM_MODE_OBJECT_MODE 0xdededede
> +#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
> +#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
> +#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
> +#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
> +#define DRM_MODE_OBJECT_ANY 0
> +
> +struct drm_mode_obj_get_properties {
> + __u64 props_ptr;
> + __u64 prop_values_ptr;
> + __u32 count_props;
> + __u32 obj_id;
> + __u32 obj_type;
> +};
> +
> +struct drm_mode_obj_set_property {
> + __u64 value;
> + __u32 prop_id;
> + __u32 obj_id;
> + __u32 obj_type;
> +};
> +
> +struct drm_mode_get_blob {
> + __u32 blob_id;
> + __u32 length;
> + __u64 data;
> +};
> +
> +struct drm_mode_fb_cmd {
> + __u32 fb_id;
> + __u32 width;
> + __u32 height;
> + __u32 pitch;
> + __u32 bpp;
> + __u32 depth;
> + /* driver specific handle */
> + __u32 handle;
> +};
> +
> +#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
> +#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
> +
> +struct drm_mode_fb_cmd2 {
> + __u32 fb_id;
> + __u32 width;
> + __u32 height;
> + __u32 pixel_format; /* fourcc code from drm_fourcc.h */
> + __u32 flags; /* see above flags */
> +
> + /*
> + * In case of planar formats, this ioctl allows up to 4
> + * buffer objects with offsets and pitches per plane.
> + * The pitch and offset order is dictated by the fourcc,
> + * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
> + *
> + * YUV 4:2:0 image with a plane of 8 bit Y samples
> + * followed by an interleaved U/V plane containing
> + * 8 bit 2x2 subsampled colour difference samples.
> + *
> + * So it would consist of Y as offsets[0] and UV as
> + * offsets[1]. Note that offsets[0] will generally
> + * be 0 (but this is not required).
> + *
> + * To accommodate tiled, compressed, etc formats, a
> + * modifier can be specified. The default value of zero
> + * indicates "native" format as specified by the fourcc.
> + * Vendor specific modifier token. Note that even though
> + * it looks like we have a modifier per-plane, we in fact
> + * do not. The modifier for each plane must be identical.
> + * Thus all combinations of different data layouts for
> + * multi plane formats must be enumerated as separate
> + * modifiers.
> + */
> + __u32 handles[4];
> + __u32 pitches[4]; /* pitch for each plane */
> + __u32 offsets[4]; /* offset of each plane */
> + __u64 modifier[4]; /* ie, tiling, compress */
> +};
> +
> +#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
> +#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
> +#define DRM_MODE_FB_DIRTY_FLAGS 0x03
> +
> +#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
> +
> +/*
> + * Mark a region of a framebuffer as dirty.
> + *
> + * Some hardware does not automatically update display contents
> + * as a hardware or software draw to a framebuffer. This ioctl
> + * allows userspace to tell the kernel and the hardware what
> + * regions of the framebuffer have changed.
> + *
> + * The kernel or hardware is free to update more then just the
> + * region specified by the clip rects. The kernel or hardware
> + * may also delay and/or coalesce several calls to dirty into a
> + * single update.
> + *
> + * Userspace may annotate the updates, the annotates are a
> + * promise made by the caller that the change is either a copy
> + * of pixels or a fill of a single color in the region specified.
> + *
> + * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
> + * the number of updated regions are half of num_clips given,
> + * where the clip rects are paired in src and dst. The width and
> + * height of each one of the pairs must match.
> + *
> + * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
> + * promises that the region specified of the clip rects is filled
> + * completely with a single color as given in the color argument.
> + */
> +
> +struct drm_mode_fb_dirty_cmd {
> + __u32 fb_id;
> + __u32 flags;
> + __u32 color;
> + __u32 num_clips;
> + __u64 clips_ptr;
> +};
> +
> +struct drm_mode_mode_cmd {
> + __u32 connector_id;
> + struct drm_mode_modeinfo mode;
> +};
> +
> +#define DRM_MODE_CURSOR_BO 0x01
> +#define DRM_MODE_CURSOR_MOVE 0x02
> +#define DRM_MODE_CURSOR_FLAGS 0x03
> +
> +/*
> + * depending on the value in flags different members are used.
> + *
> + * CURSOR_BO uses
> + * crtc_id
> + * width
> + * height
> + * handle - if 0 turns the cursor off
> + *
> + * CURSOR_MOVE uses
> + * crtc_id
> + * x
> + * y
> + */
> +struct drm_mode_cursor {
> + __u32 flags;
> + __u32 crtc_id;
> + __s32 x;
> + __s32 y;
> + __u32 width;
> + __u32 height;
> + /* driver specific handle */
> + __u32 handle;
> +};
> +
> +struct drm_mode_cursor2 {
> + __u32 flags;
> + __u32 crtc_id;
> + __s32 x;
> + __s32 y;
> + __u32 width;
> + __u32 height;
> + /* driver specific handle */
> + __u32 handle;
> + __s32 hot_x;
> + __s32 hot_y;
> +};
> +
> +struct drm_mode_crtc_lut {
> + __u32 crtc_id;
> + __u32 gamma_size;
> +
> + /* pointers to arrays */
> + __u64 red;
> + __u64 green;
> + __u64 blue;
> +};
> +
> +struct drm_color_ctm {
> + /* Conversion matrix in S31.32 format. */
> + __s64 matrix[9];
> +};
> +
> +struct drm_color_lut {
> + /*
> + * Data is U0.16 fixed point format.
> + */
> + __u16 red;
> + __u16 green;
> + __u16 blue;
> + __u16 reserved;
> +};
> +
> +#define DRM_MODE_PAGE_FLIP_EVENT 0x01
> +#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
> +#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
> +#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
> +#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
> + DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
> +#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
> + DRM_MODE_PAGE_FLIP_ASYNC | \
> + DRM_MODE_PAGE_FLIP_TARGET)
> +
> +/*
> + * Request a page flip on the specified crtc.
> + *
> + * This ioctl will ask KMS to schedule a page flip for the specified
> + * crtc. Once any pending rendering targeting the specified fb (as of
> + * ioctl time) has completed, the crtc will be reprogrammed to display
> + * that fb after the next vertical refresh. The ioctl returns
> + * immediately, but subsequent rendering to the current fb will block
> + * in the execbuffer ioctl until the page flip happens. If a page
> + * flip is already pending as the ioctl is called, EBUSY will be
> + * returned.
> + *
> + * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
> + * event (see drm.h: struct drm_event_vblank) when the page flip is
> + * done. The user_data field passed in with this ioctl will be
> + * returned as the user_data field in the vblank event struct.
> + *
> + * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
> + * 'as soon as possible', meaning that it not delay waiting for vblank.
> + * This may cause tearing on the screen.
> + *
> + * The reserved field must be zero.
> + */
> +
> +struct drm_mode_crtc_page_flip {
> + __u32 crtc_id;
> + __u32 fb_id;
> + __u32 flags;
> + __u32 reserved;
> + __u64 user_data;
> +};
> +
> +/*
> + * Request a page flip on the specified crtc.
> + *
> + * Same as struct drm_mode_crtc_page_flip, but supports new flags and
> + * re-purposes the reserved field:
> + *
> + * The sequence field must be zero unless either of the
> + * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When
> + * the ABSOLUTE flag is specified, the sequence field denotes the absolute
> + * vblank sequence when the flip should take effect. When the RELATIVE
> + * flag is specified, the sequence field denotes the relative (to the
> + * current one when the ioctl is called) vblank sequence when the flip
> + * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to
> + * make sure the vblank sequence before the target one has passed before
> + * calling this ioctl. The purpose of the
> + * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify
> + * the target for when code dealing with a page flip runs during a
> + * vertical blank period.
> + */
> +
> +struct drm_mode_crtc_page_flip_target {
> + __u32 crtc_id;
> + __u32 fb_id;
> + __u32 flags;
> + __u32 sequence;
> + __u64 user_data;
> +};
> +
> +/* create a dumb scanout buffer */
> +struct drm_mode_create_dumb {
> + __u32 height;
> + __u32 width;
> + __u32 bpp;
> + __u32 flags;
> + /* handle, pitch, size will be returned */
> + __u32 handle;
> + __u32 pitch;
> + __u64 size;
> +};
> +
> +/* set up for mmap of a dumb scanout buffer */
> +struct drm_mode_map_dumb {
> + /** Handle for the object being mapped. */
> + __u32 handle;
> + __u32 pad;
> + /**
> + * Fake offset to use for subsequent mmap call
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 offset;
> +};
> +
> +struct drm_mode_destroy_dumb {
> + __u32 handle;
> +};
> +
> +/* page-flip flags are valid, plus: */
> +#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
> +#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
> +#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
> +
> +#define DRM_MODE_ATOMIC_FLAGS (\
> + DRM_MODE_PAGE_FLIP_EVENT |\
> + DRM_MODE_PAGE_FLIP_ASYNC |\
> + DRM_MODE_ATOMIC_TEST_ONLY |\
> + DRM_MODE_ATOMIC_NONBLOCK |\
> + DRM_MODE_ATOMIC_ALLOW_MODESET)
> +
> +struct drm_mode_atomic {
> + __u32 flags;
> + __u32 count_objs;
> + __u64 objs_ptr;
> + __u64 count_props_ptr;
> + __u64 props_ptr;
> + __u64 prop_values_ptr;
> + __u64 reserved;
> + __u64 user_data;
> +};
> +
> +/**
> + * Create a new 'blob' data property, copying length bytes from data pointer,
> + * and returning new blob ID.
> + */
> +struct drm_mode_create_blob {
> + /** Pointer to data to copy. */
> + __u64 data;
> + /** Length of data to copy. */
> + __u32 length;
> + /** Return: new property ID. */
> + __u32 blob_id;
> +};
> +
> +/**
> + * Destroy a user-created blob property.
> + */
> +struct drm_mode_destroy_blob {
> + __u32 blob_id;
> +};
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#endif
> diff --git a/src/intel/drm/i915_drm.h b/src/intel/drm/i915_drm.h
> new file mode 100644
> index 00000000000..f24a80d2d42
> --- /dev/null
> +++ b/src/intel/drm/i915_drm.h
> @@ -0,0 +1,1446 @@
> +/*
> + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _UAPI_I915_DRM_H_
> +#define _UAPI_I915_DRM_H_
> +
> +#include "drm.h"
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +/* Please note that modifications to all structs defined here are
> + * subject to backwards-compatibility constraints.
> + */
> +
> +/**
> + * DOC: uevents generated by i915 on it's device node
> + *
> + * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
> + * event from the gpu l3 cache. Additional information supplied is ROW,
> + * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
> + * track of these events and if a specific cache-line seems to have a
> + * persistent error remap it with the l3 remapping tool supplied in
> + * intel-gpu-tools. The value supplied with the event is always 1.
> + *
> + * I915_ERROR_UEVENT - Generated upon error detection, currently only via
> + * hangcheck. The error detection event is a good indicator of when things
> + * began to go badly. The value supplied with the event is a 1 upon error
> + * detection, and a 0 upon reset completion, signifying no more error
> + * exists. NOTE: Disabling hangcheck or reset via module parameter will
> + * cause the related events to not be seen.
> + *
> + * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
> + * the GPU. The value supplied with the event is always 1. NOTE: Disable
> + * reset via module parameter will cause this event to not be seen.
> + */
> +#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
> +#define I915_ERROR_UEVENT "ERROR"
> +#define I915_RESET_UEVENT "RESET"
> +
> +/*
> + * MOCS indexes used for GPU surfaces, defining the cacheability of the
> + * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
> + */
> +enum i915_mocs_table_index {
> + /*
> + * Not cached anywhere, coherency between CPU and GPU accesses is
> + * guaranteed.
> + */
> + I915_MOCS_UNCACHED,
> + /*
> + * Cacheability and coherency controlled by the kernel automatically
> + * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
> + * usage of the surface (used for display scanout or not).
> + */
> + I915_MOCS_PTE,
> + /*
> + * Cached in all GPU caches available on the platform.
> + * Coherency between CPU and GPU accesses to the surface is not
> + * guaranteed without extra synchronization.
> + */
> + I915_MOCS_CACHED,
> +};
> +
> +/* Each region is a minimum of 16k, and there are at most 255 of them.
> + */
> +#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
> + * of chars for next/prev indices */
> +#define I915_LOG_MIN_TEX_REGION_SIZE 14
> +
> +typedef struct _drm_i915_init {
> + enum {
> + I915_INIT_DMA = 0x01,
> + I915_CLEANUP_DMA = 0x02,
> + I915_RESUME_DMA = 0x03
> + } func;
> + unsigned int mmio_offset;
> + int sarea_priv_offset;
> + unsigned int ring_start;
> + unsigned int ring_end;
> + unsigned int ring_size;
> + unsigned int front_offset;
> + unsigned int back_offset;
> + unsigned int depth_offset;
> + unsigned int w;
> + unsigned int h;
> + unsigned int pitch;
> + unsigned int pitch_bits;
> + unsigned int back_pitch;
> + unsigned int depth_pitch;
> + unsigned int cpp;
> + unsigned int chipset;
> +} drm_i915_init_t;
> +
> +typedef struct _drm_i915_sarea {
> + struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
> + int last_upload; /* last time texture was uploaded */
> + int last_enqueue; /* last time a buffer was enqueued */
> + int last_dispatch; /* age of the most recently dispatched buffer */
> + int ctxOwner; /* last context to upload state */
> + int texAge;
> + int pf_enabled; /* is pageflipping allowed? */
> + int pf_active;
> + int pf_current_page; /* which buffer is being displayed? */
> + int perf_boxes; /* performance boxes to be displayed */
> + int width, height; /* screen size in pixels */
> +
> + drm_handle_t front_handle;
> + int front_offset;
> + int front_size;
> +
> + drm_handle_t back_handle;
> + int back_offset;
> + int back_size;
> +
> + drm_handle_t depth_handle;
> + int depth_offset;
> + int depth_size;
> +
> + drm_handle_t tex_handle;
> + int tex_offset;
> + int tex_size;
> + int log_tex_granularity;
> + int pitch;
> + int rotation; /* 0, 90, 180 or 270 */
> + int rotated_offset;
> + int rotated_size;
> + int rotated_pitch;
> + int virtualX, virtualY;
> +
> + unsigned int front_tiled;
> + unsigned int back_tiled;
> + unsigned int depth_tiled;
> + unsigned int rotated_tiled;
> + unsigned int rotated2_tiled;
> +
> + int pipeA_x;
> + int pipeA_y;
> + int pipeA_w;
> + int pipeA_h;
> + int pipeB_x;
> + int pipeB_y;
> + int pipeB_w;
> + int pipeB_h;
> +
> + /* fill out some space for old userspace triple buffer */
> + drm_handle_t unused_handle;
> + __u32 unused1, unused2, unused3;
> +
> + /* buffer object handles for static buffers. May change
> + * over the lifetime of the client.
> + */
> + __u32 front_bo_handle;
> + __u32 back_bo_handle;
> + __u32 unused_bo_handle;
> + __u32 depth_bo_handle;
> +
> +} drm_i915_sarea_t;
> +
> +/* due to userspace building against these headers we need some compat here */
> +#define planeA_x pipeA_x
> +#define planeA_y pipeA_y
> +#define planeA_w pipeA_w
> +#define planeA_h pipeA_h
> +#define planeB_x pipeB_x
> +#define planeB_y pipeB_y
> +#define planeB_w pipeB_w
> +#define planeB_h pipeB_h
> +
> +/* Flags for perf_boxes
> + */
> +#define I915_BOX_RING_EMPTY 0x1
> +#define I915_BOX_FLIP 0x2
> +#define I915_BOX_WAIT 0x4
> +#define I915_BOX_TEXTURE_LOAD 0x8
> +#define I915_BOX_LOST_CONTEXT 0x10
> +
> +/*
> + * i915 specific ioctls.
> + *
> + * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
> + * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
> + * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
> + */
> +#define DRM_I915_INIT 0x00
> +#define DRM_I915_FLUSH 0x01
> +#define DRM_I915_FLIP 0x02
> +#define DRM_I915_BATCHBUFFER 0x03
> +#define DRM_I915_IRQ_EMIT 0x04
> +#define DRM_I915_IRQ_WAIT 0x05
> +#define DRM_I915_GETPARAM 0x06
> +#define DRM_I915_SETPARAM 0x07
> +#define DRM_I915_ALLOC 0x08
> +#define DRM_I915_FREE 0x09
> +#define DRM_I915_INIT_HEAP 0x0a
> +#define DRM_I915_CMDBUFFER 0x0b
> +#define DRM_I915_DESTROY_HEAP 0x0c
> +#define DRM_I915_SET_VBLANK_PIPE 0x0d
> +#define DRM_I915_GET_VBLANK_PIPE 0x0e
> +#define DRM_I915_VBLANK_SWAP 0x0f
> +#define DRM_I915_HWS_ADDR 0x11
> +#define DRM_I915_GEM_INIT 0x13
> +#define DRM_I915_GEM_EXECBUFFER 0x14
> +#define DRM_I915_GEM_PIN 0x15
> +#define DRM_I915_GEM_UNPIN 0x16
> +#define DRM_I915_GEM_BUSY 0x17
> +#define DRM_I915_GEM_THROTTLE 0x18
> +#define DRM_I915_GEM_ENTERVT 0x19
> +#define DRM_I915_GEM_LEAVEVT 0x1a
> +#define DRM_I915_GEM_CREATE 0x1b
> +#define DRM_I915_GEM_PREAD 0x1c
> +#define DRM_I915_GEM_PWRITE 0x1d
> +#define DRM_I915_GEM_MMAP 0x1e
> +#define DRM_I915_GEM_SET_DOMAIN 0x1f
> +#define DRM_I915_GEM_SW_FINISH 0x20
> +#define DRM_I915_GEM_SET_TILING 0x21
> +#define DRM_I915_GEM_GET_TILING 0x22
> +#define DRM_I915_GEM_GET_APERTURE 0x23
> +#define DRM_I915_GEM_MMAP_GTT 0x24
> +#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
> +#define DRM_I915_GEM_MADVISE 0x26
> +#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
> +#define DRM_I915_OVERLAY_ATTRS 0x28
> +#define DRM_I915_GEM_EXECBUFFER2 0x29
> +#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
> +#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
> +#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
> +#define DRM_I915_GEM_WAIT 0x2c
> +#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
> +#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
> +#define DRM_I915_GEM_SET_CACHING 0x2f
> +#define DRM_I915_GEM_GET_CACHING 0x30
> +#define DRM_I915_REG_READ 0x31
> +#define DRM_I915_GET_RESET_STATS 0x32
> +#define DRM_I915_GEM_USERPTR 0x33
> +#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
> +#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
> +#define DRM_I915_PERF_OPEN 0x36
> +
> +#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
> +#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
> +#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
> +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
> +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
> +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
> +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
> +#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
> +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
> +#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
> +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
> +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
> +#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
> +#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
> +#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
> +#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
> +#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
> +#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
> +#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
> +#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
> +#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
> +#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
> +#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
> +#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
> +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
> +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
> +#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
> +#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> +#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> +#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> +#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> +#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> +#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
> +#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
> +#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
> +#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
> +#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
> +#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
> +#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
> +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
> +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
> +#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
> +#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
> +#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
> +#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
> +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
> +#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
> +#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
> +#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
> +
> +/* Allow drivers to submit batchbuffers directly to hardware, relying
> + * on the security mechanisms provided by hardware.
> + */
> +typedef struct drm_i915_batchbuffer {
> + int start; /* agp offset */
> + int used; /* nr bytes in use */
> + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
> + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
> + int num_cliprects; /* mulitpass with multiple cliprects? */
> + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
> +} drm_i915_batchbuffer_t;
> +
> +/* As above, but pass a pointer to userspace buffer which can be
> + * validated by the kernel prior to sending to hardware.
> + */
> +typedef struct _drm_i915_cmdbuffer {
> + char __user *buf; /* pointer to userspace command buffer */
> + int sz; /* nr bytes in buf */
> + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
> + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
> + int num_cliprects; /* mulitpass with multiple cliprects? */
> + struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
> +} drm_i915_cmdbuffer_t;
> +
> +/* Userspace can request & wait on irq's:
> + */
> +typedef struct drm_i915_irq_emit {
> + int __user *irq_seq;
> +} drm_i915_irq_emit_t;
> +
> +typedef struct drm_i915_irq_wait {
> + int irq_seq;
> +} drm_i915_irq_wait_t;
> +
> +/* Ioctl to query kernel params:
> + */
> +#define I915_PARAM_IRQ_ACTIVE 1
> +#define I915_PARAM_ALLOW_BATCHBUFFER 2
> +#define I915_PARAM_LAST_DISPATCH 3
> +#define I915_PARAM_CHIPSET_ID 4
> +#define I915_PARAM_HAS_GEM 5
> +#define I915_PARAM_NUM_FENCES_AVAIL 6
> +#define I915_PARAM_HAS_OVERLAY 7
> +#define I915_PARAM_HAS_PAGEFLIPPING 8
> +#define I915_PARAM_HAS_EXECBUF2 9
> +#define I915_PARAM_HAS_BSD 10
> +#define I915_PARAM_HAS_BLT 11
> +#define I915_PARAM_HAS_RELAXED_FENCING 12
> +#define I915_PARAM_HAS_COHERENT_RINGS 13
> +#define I915_PARAM_HAS_EXEC_CONSTANTS 14
> +#define I915_PARAM_HAS_RELAXED_DELTA 15
> +#define I915_PARAM_HAS_GEN7_SOL_RESET 16
> +#define I915_PARAM_HAS_LLC 17
> +#define I915_PARAM_HAS_ALIASING_PPGTT 18
> +#define I915_PARAM_HAS_WAIT_TIMEOUT 19
> +#define I915_PARAM_HAS_SEMAPHORES 20
> +#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
> +#define I915_PARAM_HAS_VEBOX 22
> +#define I915_PARAM_HAS_SECURE_BATCHES 23
> +#define I915_PARAM_HAS_PINNED_BATCHES 24
> +#define I915_PARAM_HAS_EXEC_NO_RELOC 25
> +#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
> +#define I915_PARAM_HAS_WT 27
> +#define I915_PARAM_CMD_PARSER_VERSION 28
> +#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
> +#define I915_PARAM_MMAP_VERSION 30
> +#define I915_PARAM_HAS_BSD2 31
> +#define I915_PARAM_REVISION 32
> +#define I915_PARAM_SUBSLICE_TOTAL 33
> +#define I915_PARAM_EU_TOTAL 34
> +#define I915_PARAM_HAS_GPU_RESET 35
> +#define I915_PARAM_HAS_RESOURCE_STREAMER 36
> +#define I915_PARAM_HAS_EXEC_SOFTPIN 37
> +#define I915_PARAM_HAS_POOLED_EU 38
> +#define I915_PARAM_MIN_EU_IN_POOL 39
> +#define I915_PARAM_MMAP_GTT_VERSION 40
> +
> +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
> + * priorities and the driver will attempt to execute batches in priority order.
> + */
> +#define I915_PARAM_HAS_SCHEDULER 41
> +#define I915_PARAM_HUC_STATUS 42
> +
> +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
> + * synchronisation with implicit fencing on individual objects.
> + * See EXEC_OBJECT_ASYNC.
> + */
> +#define I915_PARAM_HAS_EXEC_ASYNC 43
> +
> +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
> + * both being able to pass in a sync_file fd to wait upon before executing,
> + * and being able to return a new sync_file fd that is signaled when the
> + * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
> + */
> +#define I915_PARAM_HAS_EXEC_FENCE 44
> +
> +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
> + * user specified bufffers for post-mortem debugging of GPU hangs. See
> + * EXEC_OBJECT_CAPTURE.
> + */
> +#define I915_PARAM_HAS_EXEC_CAPTURE 45
> +
> +typedef struct drm_i915_getparam {
> + __s32 param;
> + /*
> + * WARNING: Using pointers instead of fixed-size u64 means we need to write
> + * compat32 code. Don't repeat this mistake.
> + */
> + int __user *value;
> +} drm_i915_getparam_t;
> +
> +/* Ioctl to set kernel params:
> + */
> +#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
> +#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
> +#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
> +#define I915_SETPARAM_NUM_USED_FENCES 4
> +
> +typedef struct drm_i915_setparam {
> + int param;
> + int value;
> +} drm_i915_setparam_t;
> +
> +/* A memory manager for regions of shared memory:
> + */
> +#define I915_MEM_REGION_AGP 1
> +
> +typedef struct drm_i915_mem_alloc {
> + int region;
> + int alignment;
> + int size;
> + int __user *region_offset; /* offset from start of fb or agp */
> +} drm_i915_mem_alloc_t;
> +
> +typedef struct drm_i915_mem_free {
> + int region;
> + int region_offset;
> +} drm_i915_mem_free_t;
> +
> +typedef struct drm_i915_mem_init_heap {
> + int region;
> + int size;
> + int start;
> +} drm_i915_mem_init_heap_t;
> +
> +/* Allow memory manager to be torn down and re-initialized (eg on
> + * rotate):
> + */
> +typedef struct drm_i915_mem_destroy_heap {
> + int region;
> +} drm_i915_mem_destroy_heap_t;
> +
> +/* Allow X server to configure which pipes to monitor for vblank signals
> + */
> +#define DRM_I915_VBLANK_PIPE_A 1
> +#define DRM_I915_VBLANK_PIPE_B 2
> +
> +typedef struct drm_i915_vblank_pipe {
> + int pipe;
> +} drm_i915_vblank_pipe_t;
> +
> +/* Schedule buffer swap at given vertical blank:
> + */
> +typedef struct drm_i915_vblank_swap {
> + drm_drawable_t drawable;
> + enum drm_vblank_seq_type seqtype;
> + unsigned int sequence;
> +} drm_i915_vblank_swap_t;
> +
> +typedef struct drm_i915_hws_addr {
> + __u64 addr;
> +} drm_i915_hws_addr_t;
> +
> +struct drm_i915_gem_init {
> + /**
> + * Beginning offset in the GTT to be managed by the DRM memory
> + * manager.
> + */
> + __u64 gtt_start;
> + /**
> + * Ending offset in the GTT to be managed by the DRM memory
> + * manager.
> + */
> + __u64 gtt_end;
> +};
> +
> +struct drm_i915_gem_create {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_pread {
> + /** Handle for the object being read. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset into the object to read from */
> + __u64 offset;
> + /** Length of data to read */
> + __u64 size;
> + /**
> + * Pointer to write the data into.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 data_ptr;
> +};
> +
> +struct drm_i915_gem_pwrite {
> + /** Handle for the object being written to. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset into the object to write to */
> + __u64 offset;
> + /** Length of data to write */
> + __u64 size;
> + /**
> + * Pointer to read the data from.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 data_ptr;
> +};
> +
> +struct drm_i915_gem_mmap {
> + /** Handle for the object being mapped. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset in the object to map. */
> + __u64 offset;
> + /**
> + * Length of data to map.
> + *
> + * The value will be page-aligned.
> + */
> + __u64 size;
> + /**
> + * Returned pointer the data was mapped at.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 addr_ptr;
> +
> + /**
> + * Flags for extended behaviour.
> + *
> + * Added in version 2.
> + */
> + __u64 flags;
> +#define I915_MMAP_WC 0x1
> +};
> +
> +struct drm_i915_gem_mmap_gtt {
> + /** Handle for the object being mapped. */
> + __u32 handle;
> + __u32 pad;
> + /**
> + * Fake offset to use for subsequent mmap call
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 offset;
> +};
> +
> +struct drm_i915_gem_set_domain {
> + /** Handle for the object */
> + __u32 handle;
> +
> + /** New read domains */
> + __u32 read_domains;
> +
> + /** New write domain */
> + __u32 write_domain;
> +};
> +
> +struct drm_i915_gem_sw_finish {
> + /** Handle for the object */
> + __u32 handle;
> +};
> +
> +struct drm_i915_gem_relocation_entry {
> + /**
> + * Handle of the buffer being pointed to by this relocation entry.
> + *
> + * It's appealing to make this be an index into the mm_validate_entry
> + * list to refer to the buffer, but this allows the driver to create
> + * a relocation list for state buffers and not re-write it per
> + * exec using the buffer.
> + */
> + __u32 target_handle;
> +
> + /**
> + * Value to be added to the offset of the target buffer to make up
> + * the relocation entry.
> + */
> + __u32 delta;
> +
> + /** Offset in the buffer the relocation entry will be written into */
> + __u64 offset;
> +
> + /**
> + * Offset value of the target buffer that the relocation entry was last
> + * written as.
> + *
> + * If the buffer has the same offset as last time, we can skip syncing
> + * and writing the relocation. This value is written back out by
> + * the execbuffer ioctl when the relocation is written.
> + */
> + __u64 presumed_offset;
> +
> + /**
> + * Target memory domains read by this operation.
> + */
> + __u32 read_domains;
> +
> + /**
> + * Target memory domains written by this operation.
> + *
> + * Note that only one domain may be written by the whole
> + * execbuffer operation, so that where there are conflicts,
> + * the application will get -EINVAL back.
> + */
> + __u32 write_domain;
> +};
> +
> +/** @{
> + * Intel memory domains
> + *
> + * Most of these just align with the various caches in
> + * the system and are used to flush and invalidate as
> + * objects end up cached in different domains.
> + */
> +/** CPU cache */
> +#define I915_GEM_DOMAIN_CPU 0x00000001
> +/** Render cache, used by 2D and 3D drawing */
> +#define I915_GEM_DOMAIN_RENDER 0x00000002
> +/** Sampler cache, used by texture engine */
> +#define I915_GEM_DOMAIN_SAMPLER 0x00000004
> +/** Command queue, used to load batch buffers */
> +#define I915_GEM_DOMAIN_COMMAND 0x00000008
> +/** Instruction cache, used by shader programs */
> +#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
> +/** Vertex address cache */
> +#define I915_GEM_DOMAIN_VERTEX 0x00000020
> +/** GTT domain - aperture and scanout */
> +#define I915_GEM_DOMAIN_GTT 0x00000040
> +/** WC domain - uncached access */
> +#define I915_GEM_DOMAIN_WC 0x00000080
> +/** @} */
> +
> +struct drm_i915_gem_exec_object {
> + /**
> + * User's handle for a buffer to be bound into the GTT for this
> + * operation.
> + */
> + __u32 handle;
> +
> + /** Number of relocations to be performed on this buffer */
> + __u32 relocation_count;
> + /**
> + * Pointer to array of struct drm_i915_gem_relocation_entry containing
> + * the relocations to be performed in this buffer.
> + */
> + __u64 relocs_ptr;
> +
> + /** Required alignment in graphics aperture */
> + __u64 alignment;
> +
> + /**
> + * Returned value of the updated offset of the object, for future
> + * presumed_offset writes.
> + */
> + __u64 offset;
> +};
> +
> +struct drm_i915_gem_execbuffer {
> + /**
> + * List of buffers to be validated with their relocations to be
> + * performend on them.
> + *
> + * This is a pointer to an array of struct drm_i915_gem_validate_entry.
> + *
> + * These buffers must be listed in an order such that all relocations
> + * a buffer is performing refer to buffers that have already appeared
> + * in the validate list.
> + */
> + __u64 buffers_ptr;
> + __u32 buffer_count;
> +
> + /** Offset in the batchbuffer to start execution from. */
> + __u32 batch_start_offset;
> + /** Bytes used in batchbuffer from batch_start_offset */
> + __u32 batch_len;
> + __u32 DR1;
> + __u32 DR4;
> + __u32 num_cliprects;
> + /** This is a struct drm_clip_rect *cliprects */
> + __u64 cliprects_ptr;
> +};
> +
> +struct drm_i915_gem_exec_object2 {
> + /**
> + * User's handle for a buffer to be bound into the GTT for this
> + * operation.
> + */
> + __u32 handle;
> +
> + /** Number of relocations to be performed on this buffer */
> + __u32 relocation_count;
> + /**
> + * Pointer to array of struct drm_i915_gem_relocation_entry containing
> + * the relocations to be performed in this buffer.
> + */
> + __u64 relocs_ptr;
> +
> + /** Required alignment in graphics aperture */
> + __u64 alignment;
> +
> + /**
> + * When the EXEC_OBJECT_PINNED flag is specified this is populated by
> + * the user with the GTT offset at which this object will be pinned.
> + * When the I915_EXEC_NO_RELOC flag is specified this must contain the
> + * presumed_offset of the object.
> + * During execbuffer2 the kernel populates it with the value of the
> + * current GTT offset of the object, for future presumed_offset writes.
> + */
> + __u64 offset;
> +
> +#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
> +#define EXEC_OBJECT_NEEDS_GTT (1<<1)
> +#define EXEC_OBJECT_WRITE (1<<2)
> +#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
> +#define EXEC_OBJECT_PINNED (1<<4)
> +#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
> +/* The kernel implicitly tracks GPU activity on all GEM objects, and
> + * synchronises operations with outstanding rendering. This includes
> + * rendering on other devices if exported via dma-buf. However, sometimes
> + * this tracking is too coarse and the user knows better. For example,
> + * if the object is split into non-overlapping ranges shared between different
> + * clients or engines (i.e. suballocating objects), the implicit tracking
> + * by kernel assumes that each operation affects the whole object rather
> + * than an individual range, causing needless synchronisation between clients.
> + * The kernel will also forgo any CPU cache flushes prior to rendering from
> + * the object as the client is expected to be also handling such domain
> + * tracking.
> + *
> + * The kernel maintains the implicit tracking in order to manage resources
> + * used by the GPU - this flag only disables the synchronisation prior to
> + * rendering with this object in this execbuf.
> + *
> + * Opting out of implicit synhronisation requires the user to do its own
> + * explicit tracking to avoid rendering corruption. See, for example,
> + * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
> + */
> +#define EXEC_OBJECT_ASYNC (1<<6)
> +/* Request that the contents of this execobject be copied into the error
> + * state upon a GPU hang involving this batch for post-mortem debugging.
> + * These buffers are recorded in no particular order as "user" in
> + * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
> + * if the kernel supports this flag.
> + */
> +#define EXEC_OBJECT_CAPTURE (1<<7)
> +/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
> +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
> + __u64 flags;
> +
> + union {
> + __u64 rsvd1;
> + __u64 pad_to_size;
> + };
> + __u64 rsvd2;
> +};
> +
> +struct drm_i915_gem_execbuffer2 {
> + /**
> + * List of gem_exec_object2 structs
> + */
> + __u64 buffers_ptr;
> + __u32 buffer_count;
> +
> + /** Offset in the batchbuffer to start execution from. */
> + __u32 batch_start_offset;
> + /** Bytes used in batchbuffer from batch_start_offset */
> + __u32 batch_len;
> + __u32 DR1;
> + __u32 DR4;
> + __u32 num_cliprects;
> + /** This is a struct drm_clip_rect *cliprects */
> + __u64 cliprects_ptr;
> +#define I915_EXEC_RING_MASK (7<<0)
> +#define I915_EXEC_DEFAULT (0<<0)
> +#define I915_EXEC_RENDER (1<<0)
> +#define I915_EXEC_BSD (2<<0)
> +#define I915_EXEC_BLT (3<<0)
> +#define I915_EXEC_VEBOX (4<<0)
> +
> +/* Used for switching the constants addressing mode on gen4+ RENDER ring.
> + * Gen6+ only supports relative addressing to dynamic state (default) and
> + * absolute addressing.
> + *
> + * These flags are ignored for the BSD and BLT rings.
> + */
> +#define I915_EXEC_CONSTANTS_MASK (3<<6)
> +#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
> +#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
> +#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
> + __u64 flags;
> + __u64 rsvd1; /* now used for context info */
> + __u64 rsvd2;
> +};
> +
> +/** Resets the SO write offset registers for transform feedback on gen7. */
> +#define I915_EXEC_GEN7_SOL_RESET (1<<8)
> +
> +/** Request a privileged ("secure") batch buffer. Note only available for
> + * DRM_ROOT_ONLY | DRM_MASTER processes.
> + */
> +#define I915_EXEC_SECURE (1<<9)
> +
> +/** Inform the kernel that the batch is and will always be pinned. This
> + * negates the requirement for a workaround to be performed to avoid
> + * an incoherent CS (such as can be found on 830/845). If this flag is
> + * not passed, the kernel will endeavour to make sure the batch is
> + * coherent with the CS before execution. If this flag is passed,
> + * userspace assumes the responsibility for ensuring the same.
> + */
> +#define I915_EXEC_IS_PINNED (1<<10)
> +
> +/** Provide a hint to the kernel that the command stream and auxiliary
> + * state buffers already holds the correct presumed addresses and so the
> + * relocation process may be skipped if no buffers need to be moved in
> + * preparation for the execbuffer.
> + */
> +#define I915_EXEC_NO_RELOC (1<<11)
> +
> +/** Use the reloc.handle as an index into the exec object array rather
> + * than as the per-file handle.
> + */
> +#define I915_EXEC_HANDLE_LUT (1<<12)
> +
> +/** Used for switching BSD rings on the platforms with two BSD rings */
> +#define I915_EXEC_BSD_SHIFT (13)
> +#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
> +/* default ping-pong mode */
> +#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
> +#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
> +#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
> +
> +/** Tell the kernel that the batchbuffer is processed by
> + * the resource streamer.
> + */
> +#define I915_EXEC_RESOURCE_STREAMER (1<<15)
> +
> +/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
> + * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
> + * the batch.
> + *
> + * Returns -EINVAL if the sync_file fd cannot be found.
> + */
> +#define I915_EXEC_FENCE_IN (1<<16)
> +
> +/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
> + * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
> + * to the caller, and it should be close() after use. (The fd is a regular
> + * file descriptor and will be cleaned up on process termination. It holds
> + * a reference to the request, but nothing else.)
> + *
> + * The sync_file fd can be combined with other sync_file and passed either
> + * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
> + * will only occur after this request completes), or to other devices.
> + *
> + * Using I915_EXEC_FENCE_OUT requires use of
> + * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
> + * back to userspace. Failure to do so will cause the out-fence to always
> + * be reported as zero, and the real fence fd to be leaked.
> + */
> +#define I915_EXEC_FENCE_OUT (1<<17)
> +
> +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
> +
> +#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
> +#define i915_execbuffer2_set_context_id(eb2, context) \
> + (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
> +#define i915_execbuffer2_get_context_id(eb2) \
> + ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
> +
> +struct drm_i915_gem_pin {
> + /** Handle of the buffer to be pinned. */
> + __u32 handle;
> + __u32 pad;
> +
> + /** alignment required within the aperture */
> + __u64 alignment;
> +
> + /** Returned GTT offset of the buffer. */
> + __u64 offset;
> +};
> +
> +struct drm_i915_gem_unpin {
> + /** Handle of the buffer to be unpinned. */
> + __u32 handle;
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_busy {
> + /** Handle of the buffer to check for busy */
> + __u32 handle;
> +
> + /** Return busy status
> + *
> + * A return of 0 implies that the object is idle (after
> + * having flushed any pending activity), and a non-zero return that
> + * the object is still in-flight on the GPU. (The GPU has not yet
> + * signaled completion for all pending requests that reference the
> + * object.) An object is guaranteed to become idle eventually (so
> + * long as no new GPU commands are executed upon it). Due to the
> + * asynchronous nature of the hardware, an object reported
> + * as busy may become idle before the ioctl is completed.
> + *
> + * Furthermore, if the object is busy, which engine is busy is only
> + * provided as a guide. There are race conditions which prevent the
> + * report of which engines are busy from being always accurate.
> + * However, the converse is not true. If the object is idle, the
> + * result of the ioctl, that all engines are idle, is accurate.
> + *
> + * The returned dword is split into two fields to indicate both
> + * the engines on which the object is being read, and the
> + * engine on which it is currently being written (if any).
> + *
> + * The low word (bits 0:15) indicate if the object is being written
> + * to by any engine (there can only be one, as the GEM implicit
> + * synchronisation rules force writes to be serialised). Only the
> + * engine for the last write is reported.
> + *
> + * The high word (bits 16:31) are a bitmask of which engines are
> + * currently reading from the object. Multiple engines may be
> + * reading from the object simultaneously.
> + *
> + * The value of each engine is the same as specified in the
> + * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
> + * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
> + * the I915_EXEC_RENDER engine for execution, and so it is never
> + * reported as active itself. Some hardware may have parallel
> + * execution engines, e.g. multiple media engines, which are
> + * mapped to the same identifier in the EXECBUFFER2 ioctl and
> + * so are not separately reported for busyness.
> + *
> + * Caveat emptor:
> + * Only the boolean result of this query is reliable; that is whether
> + * the object is idle or busy. The report of which engines are busy
> + * should be only used as a heuristic.
> + */
> + __u32 busy;
> +};
> +
> +/**
> + * I915_CACHING_NONE
> + *
> + * GPU access is not coherent with cpu caches. Default for machines without an
> + * LLC.
> + */
> +#define I915_CACHING_NONE 0
> +/**
> + * I915_CACHING_CACHED
> + *
> + * GPU access is coherent with cpu caches and furthermore the data is cached in
> + * last-level caches shared between cpu cores and the gpu GT. Default on
> + * machines with HAS_LLC.
> + */
> +#define I915_CACHING_CACHED 1
> +/**
> + * I915_CACHING_DISPLAY
> + *
> + * Special GPU caching mode which is coherent with the scanout engines.
> + * Transparently falls back to I915_CACHING_NONE on platforms where no special
> + * cache mode (like write-through or gfdt flushing) is available. The kernel
> + * automatically sets this mode when using a buffer as a scanout target.
> + * Userspace can manually set this mode to avoid a costly stall and clflush in
> + * the hotpath of drawing the first frame.
> + */
> +#define I915_CACHING_DISPLAY 2
> +
> +struct drm_i915_gem_caching {
> + /**
> + * Handle of the buffer to set/get the caching level of. */
> + __u32 handle;
> +
> + /**
> + * Cacheing level to apply or return value
> + *
> + * bits0-15 are for generic caching control (i.e. the above defined
> + * values). bits16-31 are reserved for platform-specific variations
> + * (e.g. l3$ caching on gen7). */
> + __u32 caching;
> +};
> +
> +#define I915_TILING_NONE 0
> +#define I915_TILING_X 1
> +#define I915_TILING_Y 2
> +#define I915_TILING_LAST I915_TILING_Y
> +
> +#define I915_BIT_6_SWIZZLE_NONE 0
> +#define I915_BIT_6_SWIZZLE_9 1
> +#define I915_BIT_6_SWIZZLE_9_10 2
> +#define I915_BIT_6_SWIZZLE_9_11 3
> +#define I915_BIT_6_SWIZZLE_9_10_11 4
> +/* Not seen by userland */
> +#define I915_BIT_6_SWIZZLE_UNKNOWN 5
> +/* Seen by userland. */
> +#define I915_BIT_6_SWIZZLE_9_17 6
> +#define I915_BIT_6_SWIZZLE_9_10_17 7
> +
> +struct drm_i915_gem_set_tiling {
> + /** Handle of the buffer to have its tiling state updated */
> + __u32 handle;
> +
> + /**
> + * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> + * I915_TILING_Y).
> + *
> + * This value is to be set on request, and will be updated by the
> + * kernel on successful return with the actual chosen tiling layout.
> + *
> + * The tiling mode may be demoted to I915_TILING_NONE when the system
> + * has bit 6 swizzling that can't be managed correctly by GEM.
> + *
> + * Buffer contents become undefined when changing tiling_mode.
> + */
> + __u32 tiling_mode;
> +
> + /**
> + * Stride in bytes for the object when in I915_TILING_X or
> + * I915_TILING_Y.
> + */
> + __u32 stride;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping.
> + */
> + __u32 swizzle_mode;
> +};
> +
> +struct drm_i915_gem_get_tiling {
> + /** Handle of the buffer to get tiling state for. */
> + __u32 handle;
> +
> + /**
> + * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> + * I915_TILING_Y).
> + */
> + __u32 tiling_mode;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping.
> + */
> + __u32 swizzle_mode;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping whilst bound.
> + */
> + __u32 phys_swizzle_mode;
> +};
> +
> +struct drm_i915_gem_get_aperture {
> + /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
> + __u64 aper_size;
> +
> + /**
> + * Available space in the aperture used by i915_gem_execbuffer, in
> + * bytes
> + */
> + __u64 aper_available_size;
> +};
> +
> +struct drm_i915_get_pipe_from_crtc_id {
> + /** ID of CRTC being requested **/
> + __u32 crtc_id;
> +
> + /** pipe of requested CRTC **/
> + __u32 pipe;
> +};
> +
> +#define I915_MADV_WILLNEED 0
> +#define I915_MADV_DONTNEED 1
> +#define __I915_MADV_PURGED 2 /* internal state */
> +
> +struct drm_i915_gem_madvise {
> + /** Handle of the buffer to change the backing store advice */
> + __u32 handle;
> +
> + /* Advice: either the buffer will be needed again in the near future,
> + * or wont be and could be discarded under memory pressure.
> + */
> + __u32 madv;
> +
> + /** Whether the backing store still exists. */
> + __u32 retained;
> +};
> +
> +/* flags */
> +#define I915_OVERLAY_TYPE_MASK 0xff
> +#define I915_OVERLAY_YUV_PLANAR 0x01
> +#define I915_OVERLAY_YUV_PACKED 0x02
> +#define I915_OVERLAY_RGB 0x03
> +
> +#define I915_OVERLAY_DEPTH_MASK 0xff00
> +#define I915_OVERLAY_RGB24 0x1000
> +#define I915_OVERLAY_RGB16 0x2000
> +#define I915_OVERLAY_RGB15 0x3000
> +#define I915_OVERLAY_YUV422 0x0100
> +#define I915_OVERLAY_YUV411 0x0200
> +#define I915_OVERLAY_YUV420 0x0300
> +#define I915_OVERLAY_YUV410 0x0400
> +
> +#define I915_OVERLAY_SWAP_MASK 0xff0000
> +#define I915_OVERLAY_NO_SWAP 0x000000
> +#define I915_OVERLAY_UV_SWAP 0x010000
> +#define I915_OVERLAY_Y_SWAP 0x020000
> +#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
> +
> +#define I915_OVERLAY_FLAGS_MASK 0xff000000
> +#define I915_OVERLAY_ENABLE 0x01000000
> +
> +struct drm_intel_overlay_put_image {
> + /* various flags and src format description */
> + __u32 flags;
> + /* source picture description */
> + __u32 bo_handle;
> + /* stride values and offsets are in bytes, buffer relative */
> + __u16 stride_Y; /* stride for packed formats */
> + __u16 stride_UV;
> + __u32 offset_Y; /* offset for packet formats */
> + __u32 offset_U;
> + __u32 offset_V;
> + /* in pixels */
> + __u16 src_width;
> + __u16 src_height;
> + /* to compensate the scaling factors for partially covered surfaces */
> + __u16 src_scan_width;
> + __u16 src_scan_height;
> + /* output crtc description */
> + __u32 crtc_id;
> + __u16 dst_x;
> + __u16 dst_y;
> + __u16 dst_width;
> + __u16 dst_height;
> +};
> +
> +/* flags */
> +#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
> +#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
> +#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
> +struct drm_intel_overlay_attrs {
> + __u32 flags;
> + __u32 color_key;
> + __s32 brightness;
> + __u32 contrast;
> + __u32 saturation;
> + __u32 gamma0;
> + __u32 gamma1;
> + __u32 gamma2;
> + __u32 gamma3;
> + __u32 gamma4;
> + __u32 gamma5;
> +};
> +
> +/*
> + * Intel sprite handling
> + *
> + * Color keying works with a min/mask/max tuple. Both source and destination
> + * color keying is allowed.
> + *
> + * Source keying:
> + * Sprite pixels within the min & max values, masked against the color channels
> + * specified in the mask field, will be transparent. All other pixels will
> + * be displayed on top of the primary plane. For RGB surfaces, only the min
> + * and mask fields will be used; ranged compares are not allowed.
> + *
> + * Destination keying:
> + * Primary plane pixels that match the min value, masked against the color
> + * channels specified in the mask field, will be replaced by corresponding
> + * pixels from the sprite plane.
> + *
> + * Note that source & destination keying are exclusive; only one can be
> + * active on a given plane.
> + */
> +
> +#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
> +#define I915_SET_COLORKEY_DESTINATION (1<<1)
> +#define I915_SET_COLORKEY_SOURCE (1<<2)
> +struct drm_intel_sprite_colorkey {
> + __u32 plane_id;
> + __u32 min_value;
> + __u32 channel_mask;
> + __u32 max_value;
> + __u32 flags;
> +};
> +
> +struct drm_i915_gem_wait {
> + /** Handle of BO we shall wait on */
> + __u32 bo_handle;
> + __u32 flags;
> + /** Number of nanoseconds to wait, Returns time remaining. */
> + __s64 timeout_ns;
> +};
> +
> +struct drm_i915_gem_context_create {
> + /* output: id of new context*/
> + __u32 ctx_id;
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_context_destroy {
> + __u32 ctx_id;
> + __u32 pad;
> +};
> +
> +struct drm_i915_reg_read {
> + /*
> + * Register offset.
> + * For 64bit wide registers where the upper 32bits don't immediately
> + * follow the lower 32bits, the offset of the lower 32bits must
> + * be specified
> + */
> + __u64 offset;
> + __u64 val; /* Return value */
> +};
> +/* Known registers:
> + *
> + * Render engine timestamp - 0x2358 + 64bit - gen7+
> + * - Note this register returns an invalid value if using the default
> + * single instruction 8byte read, in order to workaround that use
> + * offset (0x2538 | 1) instead.
> + *
> + */
> +
> +struct drm_i915_reset_stats {
> + __u32 ctx_id;
> + __u32 flags;
> +
> + /* All resets since boot/module reload, for all contexts */
> + __u32 reset_count;
> +
> + /* Number of batches lost when active in GPU, for this context */
> + __u32 batch_active;
> +
> + /* Number of batches lost pending for execution, for this context */
> + __u32 batch_pending;
> +
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_userptr {
> + __u64 user_ptr;
> + __u64 user_size;
> + __u32 flags;
> +#define I915_USERPTR_READ_ONLY 0x1
> +#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> +};
> +
> +struct drm_i915_gem_context_param {
> + __u32 ctx_id;
> + __u32 size;
> + __u64 param;
> +#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
> +#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
> +#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
> +#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
> +#define I915_CONTEXT_PARAM_BANNABLE 0x5
> + __u64 value;
> +};
> +
> +enum drm_i915_oa_format {
> + I915_OA_FORMAT_A13 = 1,
> + I915_OA_FORMAT_A29,
> + I915_OA_FORMAT_A13_B8_C8,
> + I915_OA_FORMAT_B4_C8,
> + I915_OA_FORMAT_A45_B8_C8,
> + I915_OA_FORMAT_B4_C8_A16,
> + I915_OA_FORMAT_C4_B8,
> +
> + I915_OA_FORMAT_MAX /* non-ABI */
> +};
> +
> +enum drm_i915_perf_property_id {
> + /**
> + * Open the stream for a specific context handle (as used with
> + * execbuffer2). A stream opened for a specific context this way
> + * won't typically require root privileges.
> + */
> + DRM_I915_PERF_PROP_CTX_HANDLE = 1,
> +
> + /**
> + * A value of 1 requests the inclusion of raw OA unit reports as
> + * part of stream samples.
> + */
> + DRM_I915_PERF_PROP_SAMPLE_OA,
> +
> + /**
> + * The value specifies which set of OA unit metrics should be
> + * be configured, defining the contents of any OA unit reports.
> + */
> + DRM_I915_PERF_PROP_OA_METRICS_SET,
> +
> + /**
> + * The value specifies the size and layout of OA unit reports.
> + */
> + DRM_I915_PERF_PROP_OA_FORMAT,
> +
> + /**
> + * Specifying this property implicitly requests periodic OA unit
> + * sampling and (at least on Haswell) the sampling frequency is derived
> + * from this exponent as follows:
> + *
> + * 80ns * 2^(period_exponent + 1)
> + */
> + DRM_I915_PERF_PROP_OA_EXPONENT,
> +
> + DRM_I915_PERF_PROP_MAX /* non-ABI */
> +};
> +
> +struct drm_i915_perf_open_param {
> + __u32 flags;
> +#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
> +#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
> +#define I915_PERF_FLAG_DISABLED (1<<2)
> +
> + /** The number of u64 (id, value) pairs */
> + __u32 num_properties;
> +
> + /**
> + * Pointer to array of u64 (id, value) pairs configuring the stream
> + * to open.
> + */
> + __u64 properties_ptr;
> +};
> +
> +/**
> + * Enable data capture for a stream that was either opened in a disabled state
> + * via I915_PERF_FLAG_DISABLED or was later disabled via
> + * I915_PERF_IOCTL_DISABLE.
> + *
> + * It is intended to be cheaper to disable and enable a stream than it may be
> + * to close and re-open a stream with the same configuration.
> + *
> + * It's undefined whether any pending data for the stream will be lost.
> + */
> +#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
> +
> +/**
> + * Disable data capture for a stream.
> + *
> + * It is an error to try and read a stream that is disabled.
> + */
> +#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
> +
> +/**
> + * Common to all i915 perf records
> + */
> +struct drm_i915_perf_record_header {
> + __u32 type;
> + __u16 pad;
> + __u16 size;
> +};
> +
> +enum drm_i915_perf_record_type {
> +
> + /**
> + * Samples are the work horse record type whose contents are extensible
> + * and defined when opening an i915 perf stream based on the given
> + * properties.
> + *
> + * Boolean properties following the naming convention
> + * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
> + * every sample.
> + *
> + * The order of these sample properties given by userspace has no
> + * affect on the ordering of data within a sample. The order is
> + * documented here.
> + *
> + * struct {
> + * struct drm_i915_perf_record_header header;
> + *
> + * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
> + * };
> + */
> + DRM_I915_PERF_RECORD_SAMPLE = 1,
> +
> + /*
> + * Indicates that one or more OA reports were not written by the
> + * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
> + * command collides with periodic sampling - which would be more likely
> + * at higher sampling frequencies.
> + */
> + DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
> +
> + /**
> + * An error occurred that resulted in all pending OA reports being lost.
> + */
> + DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
> +
> + DRM_I915_PERF_RECORD_MAX /* non-ABI */
> +};
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#endif /* _UAPI_I915_DRM_H_ */
> diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am
> index 762aefc5542..53530827e59 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.am
> +++ b/src/mesa/drivers/dri/i965/Makefile.am
> @@ -38,9 +38,10 @@ AM_CFLAGS = \
> -I$(top_srcdir)/src/compiler/nir \
> -I$(top_builddir)/src/intel \
> -I$(top_srcdir)/src/intel \
> + -I$(top_srcdir)/src/intel/drm \
> $(DEFINES) \
> $(VISIBILITY_CFLAGS) \
> - $(LIBDRM_CFLAGS) \
> + -D__user= \
> $(VALGRIND_CFLAGS)
>
> AM_CXXFLAGS = $(AM_CFLAGS)
> --
> 2.11.0
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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