[Mesa-dev] [v2 37/39] intel/isl/gen7/hack: Use stencil vertical alignment of 8 instead of 4

[Pohjolainen, Topi]

On Tue, May 09, 2017 at 08:25:28AM +0300, Pohjolainen, Topi wrote:
> On Mon, May 08, 2017 at 03:31:55PM -0700, Jason Ekstrand wrote:
> > On Wed, May 3, 2017 at 2:22 AM, Topi Pohjolainen <topi.pohjolainen at gmail.com
> > > wrote:
> > 
> > > Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> > > ---
> > >  src/intel/isl/isl_gen7.c | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
> > > index 18687b5..cf5b377 100644
> > > --- a/src/intel/isl/isl_gen7.c
> > > +++ b/src/intel/isl/isl_gen7.c
> > > @@ -375,7 +375,11 @@ gen7_choose_valign_el(const struct isl_device *dev,
> > >         * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's
> > > API
> > >         * is more polished.
> > >         */
> > > -      require_valign4 = true;
> > > +
> > > +      /* Using valign 4 upsets all depthstencil-render-miplevels on IVB
> > > and
> > > +       * HSW. Use alignment 8 instead.
> > > +       */
> > > +      return 8;
> > >
> > 
> > I'm confused.  This seems to contradict the documentation which says that
> > valign for depth is hard-coded to 4 in the hardware.
> 
> Just as I am. It took me a while to actually try increasing the alignment - it
> was just after I compared what the current logic in i965 does. The thing here
> is not the alignment itself but the amount of space that gets allocated. I'll
> get back with more details shortly.

In intel_miptree_set_alignment() we have:

   } else if (mt->format == MESA_FORMAT_S_UINT8) {
      mt->halign = 8;
      mt->valign = brw->gen >= 7 ? 8 : 4;
   } else {

There are a few refactors it seems but I'll try to find the original commit.