[Mesa-dev] [PATCH 4/4] i965: Switch BRW_NEW_CURBE_OFFSETS to BRW_NEW_PUSH_CONSTANT_ALLOCATION.
Kenneth Graunke
kenneth at whitecape.org
Tue May 9 23:10:29 UTC 2017
The BRW_NEW_CURBE_OFFSETS dirty bit is signalled when changing the
partitioning of the Constant Buffer URB section between the various
shader stages, on Gen4-5.
BRW_NEW_PUSH_CONSTANT_ALLOCATION is basically the same thing on Gen7+.
So, save a bit, and use the new name.
---
src/mesa/drivers/dri/i965/brw_clip_state.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 5 +----
src/mesa/drivers/dri/i965/brw_curbe.c | 10 +++++-----
src/mesa/drivers/dri/i965/brw_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 -
src/mesa/drivers/dri/i965/brw_urb.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_state.c | 4 ++--
src/mesa/drivers/dri/i965/brw_wm_state.c | 4 ++--
8 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index d5fe2b547fa..35ccd2fe74f 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -86,7 +86,7 @@ brw_upload_clip_unit(struct brw_context *brw)
clip->thread3.const_urb_entry_read_length =
brw->clip.prog_data->curb_read_length;
- /* BRW_NEW_CURBE_OFFSETS */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
clip->thread3.dispatch_grf_start_reg = 1;
clip->thread3.urb_entry_read_offset = 0;
@@ -171,7 +171,7 @@ const struct brw_tracked_state brw_clip_unit = {
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_CLIP_PROG_DATA |
- BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_URB_FENCE,
},
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 723c5d6926d..100bd74f214 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -173,7 +173,6 @@ enum brw_state_id {
BRW_STATE_GEOMETRY_PROGRAM,
BRW_STATE_TESS_PROGRAMS,
BRW_STATE_VERTEX_PROGRAM,
- BRW_STATE_CURBE_OFFSETS,
BRW_STATE_REDUCED_PRIMITIVE,
BRW_STATE_PATCH_PRIMITIVE,
BRW_STATE_PRIMITIVE,
@@ -259,7 +258,6 @@ enum brw_state_id {
#define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
#define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
#define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
-#define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
#define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
#define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
#define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
@@ -955,8 +953,7 @@ struct brw_context
} urb;
- /* BRW_NEW_CURBE_OFFSETS:
- */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
struct {
GLuint wm_start; /**< pos of first wm const in CURBE buffer */
GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 7d58efb622f..139a3bcdf86 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -41,7 +41,7 @@
* quickly at thread setup time. Each individual fixed function unit's state
* (brw_vs_state.c for example) tells the hardware which subset of the CURBE
* it wants in its register space, and we calculate those areas here under the
- * BRW_NEW_CURBE_OFFSETS state flag. The brw_urb.c allocation will control
+ * BRW_NEW_PUSH_CONSTANT_ALLOCATION state flag. The brw_urb.c allocation will control
* how many CURBEs can be loaded into the hardware at once before a pipeline
* stall occurs at CMD_CONST_BUFFER time.
*
@@ -135,7 +135,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
brw->curbe.vs_start,
brw->curbe.vs_size );
- brw->ctx.NewDriverState |= BRW_NEW_CURBE_OFFSETS;
+ brw->ctx.NewDriverState |= BRW_NEW_PUSH_CONSTANT_ALLOCATION;
}
}
@@ -196,7 +196,7 @@ static void
brw_upload_constant_buffer(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_CURBE_OFFSETS */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
const GLuint sz = brw->curbe.total_size;
const GLuint bufsz = sz * 16 * sizeof(GLfloat);
gl_constant_value *buf;
@@ -216,7 +216,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
if (brw->curbe.wm_size) {
_mesa_load_state_parameters(ctx, brw->fragment_program->Parameters);
- /* BRW_NEW_CURBE_OFFSETS */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
GLuint offset = brw->curbe.wm_start * 16;
/* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
@@ -338,7 +338,7 @@ const struct brw_tracked_state brw_constant_buffer = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
- BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_PSP | /* Implicit - hardware requires this, not used above */
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 72ad044f6c7..bc3d2e5961a 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -91,7 +91,7 @@ const struct brw_tracked_state brw_gs_unit = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
- BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_FF_GS_PROG_DATA |
BRW_NEW_PROGRAM_CACHE |
BRW_NEW_URB_FENCE |
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 6c9c748b341..bcb7ff1231e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -269,7 +269,6 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
DEFINE_BIT(BRW_NEW_TESS_PROGRAMS),
DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
- DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE),
DEFINE_BIT(BRW_NEW_PRIMITIVE),
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c
index d61e713800a..1ba981a5464 100644
--- a/src/mesa/drivers/dri/i965/brw_urb.c
+++ b/src/mesa/drivers/dri/i965/brw_urb.c
@@ -213,7 +213,7 @@ const struct brw_tracked_state brw_recalculate_urb_fence = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BLORP |
- BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_SF_PROG_DATA |
BRW_NEW_VS_PROG_DATA,
},
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index df34a466ea1..fafe305f4f7 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -97,7 +97,7 @@ brw_upload_vs_unit(struct brw_context *brw)
vs->thread3.dispatch_grf_start_reg = prog_data->dispatch_grf_start_reg;
vs->thread3.urb_entry_read_offset = 0;
- /* BRW_NEW_CURBE_OFFSETS */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
/* BRW_NEW_URB_FENCE */
@@ -182,8 +182,8 @@ const struct brw_tracked_state brw_vs_unit = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
- BRW_NEW_CURBE_OFFSETS |
BRW_NEW_PROGRAM_CACHE |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_SAMPLER_STATE_TABLE |
BRW_NEW_URB_FENCE |
BRW_NEW_VS_PROG_DATA,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f018fddbe83..69bbeb26d44 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -148,7 +148,7 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->thread3.urb_entry_read_offset = 0;
wm->thread3.const_urb_entry_read_length =
prog_data->base.curb_read_length;
- /* BRW_NEW_CURBE_OFFSETS */
+ /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
if (brw->gen == 5)
@@ -263,7 +263,7 @@ const struct brw_tracked_state brw_wm_unit = {
_NEW_POLYGONSTIPPLE,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
- BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_PROGRAM_CACHE |
--
2.12.2
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