[Mesa-dev] [PATCH 4/5] radeonsi: reduce the number of generics for shader IO unique indices

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

This is a high as possible while still allowing to merge the bitfields
with the next commit.

For OpenGL, 32 would be sufficient. Nine apparently uses (much!) higher
indices than. Indices that are out of bound don't hurt for VS-PS
pipelines, except that the VS output kill optimization is not applied.
---
 src/gallium/drivers/radeonsi/si_shader.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index cf97a71..3075900 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -141,21 +141,21 @@
 #include "util/u_queue.h"
 #include "si_state.h"
 
 struct ac_shader_binary;
 
 #define SI_MAX_VS_OUTPUTS	40
 
 /* Shader IO unique indices are supported for TGSI_SEMANTIC_GENERIC with an
  * index smaller than this.
  */
-#define SI_MAX_IO_GENERIC       60
+#define SI_MAX_IO_GENERIC       46
 
 /* SGPR user data indices */
 enum {
 	/* GFX9 merged shaders have RW_BUFFERS among the first 8 system SGPRs,
 	 * and these two are used for other purposes.
 	 */
 	SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
 	SI_SGPR_RW_BUFFERS_HI,
 	SI_SGPR_CONST_BUFFERS,
 	SI_SGPR_CONST_BUFFERS_HI,
-- 
2.9.3