[Mesa-dev] [PATCH 21/24] i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

[Anuj Phogat]

v1: By Ben Widawsky <benjamin.widawsky at intel.com>
v2: Add the restriction for GS, HS and DS and make sure
    the allocated sizes are not multiple of 3.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: Ben Widawsky <benjamin.widawsky at intel.com>
---
 src/mesa/drivers/dri/i965/gen7_urb.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 028161d..dc6826a 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -194,6 +194,17 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
       entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
    }
 
+   /* For Cannonlake:
+    * Software shall not program an allocation size that specifies a size
+    * that is a multiple of 3 64B (512-bit) cachelines.
+    */
+   if (brw->gen == 10) {
+      for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+         if (entry_size[i] % 3 == 0)
+            entry_size[i]++;
+      }
+   }
+
    /* If we're just switching between programs with the same URB requirements,
     * skip the rest of the logic.
     */
@@ -224,6 +235,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 
    BEGIN_BATCH(8);
    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+      assert(brw->gen != 10 || entry_size[i] % 3);
       OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
       OUT_BATCH(entries[i] |
                 ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-- 
2.9.3