[Mesa-dev] [PATCH] i965/blorp: Do and end-of-pipe sync on both sides of fast-clear ops

[Pohjolainen, Topi]

On Mon, May 15, 2017 at 07:55:46AM -0700, Jason Ekstrand wrote:
> We've discovered in the Vulkan driver that simply doing the end-of-pipe
> sync afterwards is insufficient.  The specific requirement stated in the
> PRM is that you have to do one every time you transition between the
> tree modes of "clear", "render", and "resolve".  This is GL, so we could
> track it but any attempt to do so would most likely get it wrong.  For
> now, it's easier to just assume that every fast-clear op is an island
> and do the sync both before and after.
> 
> This also removes the unneeded flush and stall after slow-clear
> operations.
> 
> Cc: "17.0 17.1" <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 56 ++++++++++++++++++++++++-----------
>  1 file changed, 38 insertions(+), 18 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
> index b69cb4f..ebc4612 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -876,6 +876,22 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
>        DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
>            irb->mt, irb->mt_level, irb->mt_layer, num_layers);
>  
> +      /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
> +       *
> +       *    "Any transition from any value in {Clear, Render, Resolve} to a
> +       *    different value in {Clear, Render, Resolve} requires end of pipe
> +       *    synchronization."

I've been meaning to ask should we add some clarification when we refer to
end-of-pipe sync but don't actually do exactly what the spec says. According
to spec there should be also a write just after the flush. I have quite a bit
of details in:

https://lists.freedesktop.org/archives/mesa-dev/2017-February/144813.html