[Mesa-dev] [PATCH] gallium/radeon: use a top-of-pipe timestamp for the start of TIME_ELAPSED

[Nicolai Hähnle]

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 15.05.2017 17:33, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
>  src/amd/common/r600d_common.h           | 11 +++++++++++
>  src/gallium/drivers/radeon/r600_query.c | 21 +++++++++++++++++++--
>  2 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h
> index 3fdfb7c..3374475 100644
> --- a/src/amd/common/r600d_common.h
> +++ b/src/amd/common/r600d_common.h
> @@ -47,20 +47,31 @@
>  #define		STRMOUT_STORE_BUFFER_FILLED_SIZE	1
>  #define		STRMOUT_OFFSET_SOURCE(x)	(((unsigned)(x) & 0x3) << 1)
>  #define			STRMOUT_OFFSET_FROM_PACKET		0
>  #define			STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE	1
>  #define			STRMOUT_OFFSET_FROM_MEM			2
>  #define			STRMOUT_OFFSET_NONE			3
>  #define		STRMOUT_SELECT_BUFFER(x)	(((unsigned)(x) & 0x3) << 8)
>  #define PKT3_WAIT_REG_MEM                      0x3C
>  #define		WAIT_REG_MEM_EQUAL		3
>  #define         WAIT_REG_MEM_MEM_SPACE(x)       (((unsigned)(x) & 0x3) << 4)
> +#define PKT3_COPY_DATA			       0x40
> +#define		COPY_DATA_SRC_SEL(x)		((x) & 0xf)
> +#define			COPY_DATA_REG		0
> +#define			COPY_DATA_MEM		1
> +#define                 COPY_DATA_PERF          4
> +#define                 COPY_DATA_IMM           5
> +#define                 COPY_DATA_TIMESTAMP     9
> +#define		COPY_DATA_DST_SEL(x)		(((unsigned)(x) & 0xf) << 8)
> +#define                 COPY_DATA_MEM_ASYNC     5
> +#define		COPY_DATA_COUNT_SEL		(1 << 16)
> +#define		COPY_DATA_WR_CONFIRM		(1 << 20)
>  #define PKT3_EVENT_WRITE                       0x46
>  #define PKT3_EVENT_WRITE_EOP                   0x47
>  #define         EOP_DATA_SEL(x)                         ((x) << 29)
>  		/* 0 - discard
>  		 * 1 - send low 32bit data
>  		 * 2 - send 64bit data
>  		 * 3 - send 64bit GPU counter value
>  		 * 4 - send 64bit sys counter value
>  		 */
>  #define PKT3_RELEASE_MEM                       0x49 /* GFX9+ */
> diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
> index 9878745..61fd662 100644
> --- a/src/gallium/drivers/radeon/r600_query.c
> +++ b/src/gallium/drivers/radeon/r600_query.c
> @@ -682,22 +682,39 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
>  	case PIPE_QUERY_PRIMITIVES_EMITTED:
>  	case PIPE_QUERY_PRIMITIVES_GENERATED:
>  	case PIPE_QUERY_SO_STATISTICS:
>  	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, va >> 32);
>  		break;
>  	case PIPE_QUERY_TIME_ELAPSED:
> -		r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
> -					 0, 3, NULL, va, 0, 0);
> +		if (ctx->chip_class >= SI) {
> +			/* Write the timestamp from the CP not waiting for
> +			 * outstanding draws (top-of-pipe).
> +			 */
> +			radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
> +			radeon_emit(cs, COPY_DATA_COUNT_SEL |
> +					COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
> +					COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
> +			radeon_emit(cs, 0);
> +			radeon_emit(cs, 0);
> +			radeon_emit(cs, va);
> +			radeon_emit(cs, va >> 32);
> +		} else {
> +			/* Write the timestamp after the last draw is done.
> +			 * (bottom-of-pipe)
> +			 */
> +			r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
> +						 0, 3, NULL, va, 0, 0);
> +		}
>  		break;
>  	case PIPE_QUERY_PIPELINE_STATISTICS:
>  		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
>  		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
>  		radeon_emit(cs, va);
>  		radeon_emit(cs, va >> 32);
>  		break;
>  	default:
>  		assert(0);
>  	}
>


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