[Mesa-dev] [PATCH 00/43] BLORP for everyone!
Jason Ekstrand
jason at jlekstrand.net
Tue May 16 22:44:54 UTC 2017
When Sandy Bridge came out, surface state management suddenly became
significantly more complicated because of HiZ, MSAA, and separate stencil.
In order to deal with all of these complications, Paul Berry write BLORP
which is a blit framework that's capable of handling all of the exotic
cases we have to deal with in a modern Intel driver. As time went on,
blorp was ported to Ivy Bridge and then Haswell. At Broadwell, we tried to
get away from blorp but eventually decided that having one more copy of
state setup wasn't so bad compared to dealing with meta so it was brought
forward to gen8-9. However, it has never been back-ported to gen4-5...
Until today!
Why should we do this? For one thing, it's actually less code. The patch
which actually adds gen4 support to blorp is around 300 LOC. If you add on
the patch which adds SF program support, you get another 50. On the other
hand, the meta PBO upload path is 450 lines of code all by itself and that
doesn't include the DD table entry or the code we have to carry in i965 to
support it. Secondly, it lets us unify a bunch of gen6 and gen4 stuff.
You can already see in this series that I delete an entire blitframebuffers
implementation because we were carrying 2 just so gen4-5 could have its
own.
This series doesn't actually get everything converted over but it does
convert enough that I'm reasonably confident that it all works. In the
process, this series fixes 12 tests: 2 on ILK, 2 on g45, and 8 on i965.
I intentionally did most of the BLORP port in a single patch. This way
it's easy for the reviewer to see both the new state setup code as well as
the few modifications that have to be made to blorp_blit and blorp_clear to
handle new cases created by gen4.
The only thing I'm not entirely happy with is the way color write disables
get plumbed through ISL. That said, I don't come up with a better
mechanism so I'm fine with what I have.
This series is available here:
https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/blorp-gen4
Happy reviewing!
Jason Ekstrand (43):
i965/blorp: Do and end-of-pipe sync on both sides of fast-clear ops
i965: Use blorp_copy for doing r8 stencil updates on HSW
intel/blorp: Move the gen7 stencil format workaround to blorp_blit
i965/miptree: Take first_level into account when converting to ISL
i965/blorp: Properly handle mt->first_level
intel/isl: Don't request space for stencil/hiz packets unless needed
intel/isl: Add support for gen4 cube maps to get_image_offset_sa
intel/isl: Add support for setting component write disables
intel/isl: Add gen4_filter_tiling
intel/genxml: Make a bunch of things offsets on gen4-5
intel/gensml: Suffix KSP0 fields on Iron Lake
intel/genxml: Sampler state is a pointer on gen4-5
intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5
intel/genxml: Add SAMPLER_STATE to gen 4.5
intel/genxml: Iron Lake doesn't support non-normalized sampler
coordinates
intel/genxml: Use the right subtype for VF_STATISTICS on gen4
intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5
intel/decoder: Handle gen4 VF_STATISTICS and PIPELINE_SELECT
intel/decoder: Handle the BLT ring in gen_group_get_length
intel/compiler: Make brw_disasm take const assembly
i965/sf: make brw_sf_prog_key::interp_mode an array
i965/clip: Make brw_clip_prog_key::interp_mode an array
i965: Move SF compilation to the compiler
i965: Move clip program compilation to the compiler
intel/blorp/blit: Add support for normalized coordinates
intel/blorp: Pull the pipeline bits of blorp_exec into a helper
intel/blorp: Delete isl_to_gen_ds_surfype
intel/blorp: Don't use ffma directly
intel/blorp: Re-arrange blorp_genX_exec.h
intel/blorp: Make the common genX_blorp_exec code gen4-safe
intel/blorp: Rename emit_viewport_state to emit_cc_viewport
intel/blorp: Use designated initializers to set up VERTEX_ELEMENTS
intel/blorp: Make convert_to_single_slice available outside blorp_blit
intel/blorp: Add support for gen4-5 SF programs
i965/gen4: Expose the guts of URB recalculation as a helper
intel/blorp: Set additional brw_wm_prog_key fields on gen4-5
i965: Add blorp support for gen4-5
intel/blorp: Assert that no one tries to blit combined depth stencil
i965: Use blorp for color blits on gen4-5
i965: Use BLORP for color clears on gen4-5
i965: Round copy size to the nearest block in intel_miptree_copy
i965: Use blorp for CopyImageSubData on gen4-5
i965/blorp: Support copyteximage on gen4-5
src/intel/Makefile.sources | 8 +
src/intel/blorp/blorp.c | 82 ++-
src/intel/blorp/blorp_blit.c | 75 ++-
src/intel/blorp/blorp_clear.c | 33 +-
src/intel/blorp/blorp_genX_exec.h | 651 ++++++++++++---------
src/intel/blorp/blorp_priv.h | 18 +-
src/intel/common/gen_decoder.c | 13 +-
.../drivers/dri/i965 => intel/compiler}/brw_clip.h | 38 +-
.../dri/i965 => intel/compiler}/brw_clip_line.c | 6 -
.../dri/i965 => intel/compiler}/brw_clip_point.c | 4 -
.../dri/i965 => intel/compiler}/brw_clip_tri.c | 8 +-
.../i965 => intel/compiler}/brw_clip_unfilled.c | 39 +-
.../dri/i965 => intel/compiler}/brw_clip_util.c | 6 -
src/intel/compiler/brw_compile_clip.c | 96 +++
.../compiler/brw_compile_sf.c} | 185 ++++--
src/intel/compiler/brw_compiler.h | 114 ++++
src/intel/compiler/brw_disasm.c | 20 +-
src/intel/compiler/brw_eu.c | 4 +-
src/intel/compiler/brw_eu.h | 6 +-
src/intel/compiler/brw_eu_defines.h | 2 +
src/intel/genxml/gen4.xml | 20 +-
src/intel/genxml/gen45.xml | 79 ++-
src/intel/genxml/gen5.xml | 25 +-
src/intel/isl/isl.c | 39 +-
src/intel/isl/isl.h | 20 +
src/intel/isl/isl_gen4.c | 51 ++
src/intel/isl/isl_gen4.h | 5 +
src/intel/isl/isl_surface_state.c | 6 +
src/intel/vulkan/genX_blorp_exec.c | 5 +-
src/mesa/drivers/dri/i965/Makefile.sources | 11 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 97 ++-
src/mesa/drivers/dri/i965/brw_blorp.h | 6 +
src/mesa/drivers/dri/i965/brw_clear.c | 3 +-
src/mesa/drivers/dri/i965/brw_clip.c | 110 +---
src/mesa/drivers/dri/i965/brw_context.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.h | 23 +-
src/mesa/drivers/dri/i965/brw_defines.h | 9 -
src/mesa/drivers/dri/i965/brw_sf.c | 93 +--
src/mesa/drivers/dri/i965/brw_sf.h | 111 ----
src/mesa/drivers/dri/i965/brw_sf_state.c | 1 -
src/mesa/drivers/dri/i965/brw_urb.c | 15 +-
src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 197 +++++++
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
src/mesa/drivers/dri/i965/intel_blit.c | 4 +-
src/mesa/drivers/dri/i965/intel_copy_image.c | 140 +----
src/mesa/drivers/dri/i965/intel_fbo.c | 66 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 +-
48 files changed, 1551 insertions(+), 1033 deletions(-)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip.h (86%)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip_line.c (99%)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip_point.c (95%)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip_tri.c (99%)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip_unfilled.c (94%)
rename src/{mesa/drivers/dri/i965 => intel/compiler}/brw_clip_util.c (99%)
create mode 100644 src/intel/compiler/brw_compile_clip.c
rename src/{mesa/drivers/dri/i965/brw_sf_emit.c => intel/compiler/brw_compile_sf.c} (79%)
delete mode 100644 src/mesa/drivers/dri/i965/brw_sf.h
create mode 100644 src/mesa/drivers/dri/i965/gen4_blorp_exec.h
--
2.5.0.400.gff86faf
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