[Mesa-dev] [PATCH 08/43] intel/isl: Add support for setting component write disables

[Jason Ekstrand]

---
 src/intel/isl/isl.h               | 20 ++++++++++++++++++++
 src/intel/isl/isl_surface_state.c |  6 ++++++
 2 files changed, 26 insertions(+)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 7778551..f89ba50 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -576,6 +576,21 @@ typedef uint64_t isl_surf_usage_flags_t;
 /** @} */
 
 /**
+ * @defgroup Channel Mask
+ *
+ * These #define values are chosen to match the values of
+ * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
+ *
+ * @{
+ */
+typedef uint8_t isl_channel_mask_t;
+#define ISL_CHANNEL_BLUE_BIT  (1 << 0)
+#define ISL_CHANNEL_GREEN_BIT (1 << 1)
+#define ISL_CHANNEL_RED_BIT   (1 << 2)
+#define ISL_CHANNEL_ALPHA_BIT (1 << 3)
+/** @} */
+
+/**
  * @brief A channel select (also known as texture swizzle) value
  */
 enum isl_channel_select {
@@ -995,6 +1010,11 @@ struct isl_surf_fill_state_info {
     */
    union isl_color_value clear_color;
 
+   /**
+    * Surface write disables for gen4-5
+    */
+   isl_channel_mask_t write_disables;
+
    /* Intra-tile offset */
    uint16_t x_offset_sa, y_offset_sa;
 };
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index fa46469..d63b245 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -256,6 +256,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 
    s.SurfaceFormat = info->view->format;
 
+#if GEN_GEN <= 5
+   s.ColorBufferComponentWriteDisables = info->write_disables;
+#else
+   assert(info->write_disables == 0);
+#endif
+
 #if GEN_IS_HASWELL
    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 #endif
-- 
2.5.0.400.gff86faf