[Mesa-dev] [PATCH 05/15] radv: remove radeon_surf_level::dcc_enabled

Nicolai Hähnle nhaehnle at gmail.com
Thu May 18 09:53:47 UTC 2017


From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Like radeonsi; replace with radeon_surf::num_dcc_levels.
---
 src/amd/vulkan/radv_device.c                       | 2 +-
 src/amd/vulkan/radv_image.c                        | 2 +-
 src/amd/vulkan/radv_meta_resolve.c                 | 2 +-
 src/amd/vulkan/radv_radeon_winsys.h                | 3 ++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 ++--
 5 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 921b8e4..2c7a680 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2729,21 +2729,21 @@ radv_initialise_color_surface(struct radv_device *device,
 		S_028C70_NUMBER_TYPE(ntype) |
 		S_028C70_ENDIAN(endian);
 	if (iview->image->info.samples > 1)
 		if (iview->image->fmask.size)
 			cb->cb_color_info |= S_028C70_COMPRESSION(1);
 
 	if (iview->image->cmask.size &&
 	    !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
 		cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
 
-	if (iview->image->surface.dcc_size && level_info->dcc_enabled)
+	if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
 		cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
 
 	if (device->physical_device->rad_info.chip_class >= VI) {
 		unsigned max_uncompressed_block_size = 2;
 		if (iview->image->info.samples > 1) {
 			if (iview->image->surface.bpe == 1)
 				max_uncompressed_block_size = 0;
 			else if (iview->image->surface.bpe == 2)
 				max_uncompressed_block_size = 1;
 		}
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index cd1db12..8880e5c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -205,21 +205,21 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 	state[6] &= C_008F28_COMPRESSION_EN;
 
 	assert(!(va & 255));
 
 	state[0] = va >> 8;
 	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 	state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
 							     is_stencil));
 	state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
 
-	if (image->surface.dcc_size && image->surface.level[first_level].dcc_enabled) {
+	if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
 		state[6] |= S_008F28_COMPRESSION_EN(1);
 		state[7] = (gpu_address +
 			    image->dcc_offset +
 			    base_level_info->dcc_offset) >> 8;
 	}
 }
 
 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
 			     unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
 {
diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index fca6005..44e6402 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -308,21 +308,21 @@ enum radv_resolve_method {
 	RESOLVE_COMPUTE,
 	RESOLVE_FRAGMENT,
 };
 
 static void radv_pick_resolve_method_images(struct radv_image *src_image,
 					    struct radv_image *dest_image,
 					    enum radv_resolve_method *method)
 
 {
 	if (dest_image->surface.micro_tile_mode != src_image->surface.micro_tile_mode) {
-		if (dest_image->surface.level[0].dcc_enabled)
+		if (dest_image->surface.num_dcc_levels > 0)
 			*method = RESOLVE_FRAGMENT;
 		else
 			*method = RESOLVE_COMPUTE;
 	}
 }
 
 void radv_CmdResolveImage(
 	VkCommandBuffer                             cmd_buffer_h,
 	VkImage                                     src_image_h,
 	VkImageLayout                               src_image_layout,
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index df582d8..365ff11 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -164,34 +164,35 @@ struct radeon_surf_info {
 	uint16_t array_size;
 };
 
 struct radeon_surf_level {
 	uint64_t                    offset;
 	uint64_t                    slice_size;
 	uint32_t                    nblk_x;
 	uint32_t                    nblk_y;
 	uint32_t                    nblk_z;
 	uint32_t                    mode;
-	bool                        dcc_enabled;
 	uint64_t                    dcc_offset;
 	uint64_t                    dcc_fast_clear_size;
 };
 
 
 /* surface defintions from the winsys */
 struct radeon_surf {
 	/* These are inputs to the calculator. */
 	uint32_t                    blk_w;
 	uint32_t                    blk_h;
 	uint32_t                    bpe;
 	uint32_t                    flags;
 
+	unsigned                    num_dcc_levels:4;
+
 	/* These are return values. Some of them can be set by the caller, but
 	 * they will be treated as hints (e.g. bankw, bankh) and might be
 	 * changed by the calculator.
 	 */
 	uint64_t                    bo_size;
 	uint64_t                    bo_alignment;
 	/* This applies to EG and later. */
 	uint32_t                    bankw;
 	uint32_t                    bankh;
 	uint32_t                    mtilea;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index f8e22da..ab1f952 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -226,39 +226,38 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 
 	if (is_stencil)
 		surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 	else
 		surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 
 	surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 
 	/* Clear DCC fields at the beginning. */
 	surf_level->dcc_offset = 0;
-	surf_level->dcc_enabled = false;
 
 	/* The previous level's flag tells us if we can use DCC for this level. */
 	if (AddrSurfInfoIn->flags.dccCompatible &&
 	    (level == 0 || AddrDccOut->subLvlCompressible)) {
 		AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 		AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 		AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 		AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 		AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 
 		ret = AddrComputeDccInfo(addrlib,
 					 AddrDccIn,
 					 AddrDccOut);
 
 		if (ret == ADDR_OK) {
 			surf_level->dcc_offset = surf->dcc_size;
 			surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
-			surf_level->dcc_enabled = true;
+			surf->num_dcc_levels = level + 1;
 			surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 			surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 		}
 	}
 
 	if (!is_stencil && AddrSurfInfoIn->flags.depth &&
 	    surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
 		ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 		ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 		AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
@@ -469,20 +468,21 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 		} else {
 			if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 				AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 			else
 				AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 			AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 		}
 	}
 
 	surf->bo_size = 0;
+	surf->num_dcc_levels = 0;
 	surf->dcc_size = 0;
 	surf->dcc_alignment = 1;
 	surf->htile_size = surf->htile_slice_size = 0;
 	surf->htile_alignment = 1;
 
 	/* Calculate texture layout information. */
 	for (level = 0; level <= last_level; level++) {
 		r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
 				       &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
 		if (r)
-- 
2.9.3



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