[Mesa-dev] [PATCH v13 34/36] i965: Add tiling mode to BO import

[Daniel Stone]

When importing a dmabuf, verify that the tiling mode matches what was
expected.

Signed-off-by: Daniel Stone <daniels at collabora.com>
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c   | 12 ++++++++++--
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  3 ++-
 src/mesa/drivers/dri/i965/intel_screen.c |  5 +++--
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 2f17934700..56cf979bef 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1014,7 +1014,7 @@ brw_bo_get_tiling(struct brw_bo *bo, uint32_t *tiling_mode,
 
 struct brw_bo *
 brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
-                             int size)
+                             int size, uint32_t tiling)
 {
    int ret;
    uint32_t handle;
@@ -1071,8 +1071,16 @@ brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
    if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
       goto err;
 
-   bo->tiling_mode = get_tiling.tiling_mode;
    bo->swizzle_mode = get_tiling.swizzle_mode;
+   bo->tiling_mode = get_tiling.tiling_mode;
+
+   /* If the import explicitly specifies a tiling mode, verify that it matches;
+    * TILING_X is taken as the default where a mismatch is not fatal, and means
+    * to infer the real tiling mode. */
+   if (tiling != I915_TILING_X &&
+       (bo->tiling_mode != tiling && bo->tiling_mode != I915_TILING_NONE))
+      goto err;
+
    /* XXX stride is unknown */
 
 out:
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 56ec206d30..0a85d9d1c9 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -272,7 +272,8 @@ void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id);
 
 int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
 struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
-                                            int prime_fd, int size);
+                                            int prime_fd, int size,
+                                            uint32_t tiling);
 
 int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
                  uint64_t *result);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 06e2301d33..1238afb5cb 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -927,6 +927,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
    struct intel_screen *screen = dri_screen->driverPrivate;
    struct intel_image_format *f;
    __DRIimage *image;
+   uint32_t tiling = I915_TILING_X; /* default to X-tiling */
    int i, index;
 
    if (fds == NULL || num_fds < 1)
@@ -963,8 +964,8 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
          size = end;
    }
 
-   image->bo = brw_bo_gem_create_from_prime(screen->bufmgr,
-                                                  fds[0], size);
+   image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size,
+                                            tiling);
    if (image->bo == NULL) {
       free(image);
       return NULL;
-- 
2.13.0