[Mesa-dev] i965/gen4: Depth buffer setup cleanup

[Topi Pohjolainen]

First this series removes logic considering separate stencil 
gen < 6 only code paths (where we always use combined
depth-stencil).

Then patch 5 simplifies the workaround we need for aligning
depth buffer. On gen < 6 there is no support for telling which
mip-level to draw and hence the driver needs to offset the
buffer accordingly. Unfortunately hardware also requires
aligned buffer offsets forcing the driver to use temporary
aligned copies (which are reconciled back into the mipmapped
buffer later on).

However, in case of combined depth-stencil there are cases
where there is no depth attachment but stencil only (which
is also backed by combined depth-stencil). In those cases
current logic fails to offset the buffer correctly when the
miplevel is already aligned and doesn't need a copy. Driver
correctly sets the intra tile offsets (g45 and ilk) but
leaves the page aligned offset zero. This gets fixed
by patch 5.
I considered fixing this first and only then do the
cleanups but unfortunately that would make ugly even
uglier.

Topi Pohjolainen (6):
  i965/gen4: Remove non-existing stencil and hiz buffer setup
  i965/gen4: Remove redundant check for depth when rebasing stencil
  i965/gen4: Simplify depth/stencil invalidate check
  i965: Drop depth/stencil miptree pointers in alignment workaround
  i965/gen4: Refactor depth/stencil rebase
  i965/gen4: Tell briefly how workaround depth gets reconciled

 src/mesa/drivers/dri/i965/brw_context.h    |   9 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c | 430 ++++++-----------------------
 2 files changed, 88 insertions(+), 351 deletions(-)

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2.9.3