[Mesa-dev] [PATCH 6/6] i965/gen4: Tell briefly how workaround depth gets reconciled

[Topi Pohjolainen]

CC: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 85050ce..fe021b0 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -165,6 +165,13 @@ rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
       perf_debug("HW workaround: blitting depth level %d to a temporary "
                  "to fix alignment (depth tile offset %d,%d)\n",
                  irb->mt_level, tile_x, tile_y);
+
+      /* Create new miptree representing single "irb->mt_level" only and
+       * make renderbuffer point this instead of the full miptree. Note that
+       * the underlying texture object still carries reference to the original
+       * full mipmap tree and intel_finalize_mipmap_tree() will eventually
+       * merge these two.
+       */
       intel_renderbuffer_move_to_temp(brw, irb, invalidate);
 
       /* Get the new offset. */
-- 
2.9.3