[Mesa-dev] [PATCH] intel/compiler: Make use of IS_DWORD macro
Anuj Phogat
anuj.phogat at gmail.com
Tue May 23 20:51:30 UTC 2017
This patch makes non-functional changes.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
src/intel/compiler/brw_eu_defines.h | 3 +++
src/intel/compiler/brw_eu_emit.c | 24 +++++++-----------------
src/intel/compiler/brw_fs.cpp | 3 +--
src/intel/compiler/brw_fs_cmod_propagation.cpp | 3 +--
src/intel/compiler/brw_fs_copy_propagation.cpp | 3 +--
src/intel/compiler/brw_fs_generator.cpp | 6 ++----
src/intel/compiler/brw_fs_nir.cpp | 2 +-
src/intel/compiler/brw_vec4.cpp | 5 -----
src/intel/compiler/brw_vec4_cmod_propagation.cpp | 3 +--
src/intel/compiler/brw_vec4_generator.cpp | 2 +-
10 files changed, 18 insertions(+), 36 deletions(-)
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index ccc838d..9e969f2 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -48,6 +48,9 @@
#define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
+#define IS_DWORD(reg) \
+ (reg.type == BRW_REGISTER_TYPE_UD || \
+ reg.type == BRW_REGISTER_TYPE_D)
#define _3DPRIM_POINTLIST 0x01
#define _3DPRIM_LINELIST 0x02
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 231d6fd..7434610 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -959,8 +959,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
assert(dest.type == BRW_REGISTER_TYPE_F ||
dest.type == BRW_REGISTER_TYPE_DF ||
- dest.type == BRW_REGISTER_TYPE_D ||
- dest.type == BRW_REGISTER_TYPE_UD);
+ IS_DWORD(dest));
if (devinfo->gen == 6) {
brw_inst_set_3src_dst_reg_file(devinfo, inst,
dest.file == BRW_MESSAGE_REGISTER_FILE);
@@ -1158,9 +1157,7 @@ brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0)
if (devinfo->gen == 7 && !devinfo->is_haswell &&
brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1 &&
dest.type == BRW_REGISTER_TYPE_DF &&
- (src0.type == BRW_REGISTER_TYPE_F ||
- src0.type == BRW_REGISTER_TYPE_D ||
- src0.type == BRW_REGISTER_TYPE_UD) &&
+ (src0.type == BRW_REGISTER_TYPE_F || IS_DWORD(src0)) &&
!has_scalar_region(src0)) {
assert(src0.vstride == BRW_VERTICAL_STRIDE_4 &&
src0.width == BRW_WIDTH_4 &&
@@ -1182,15 +1179,13 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest,
if (src0.type == BRW_REGISTER_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
- assert(src1.type != BRW_REGISTER_TYPE_UD);
- assert(src1.type != BRW_REGISTER_TYPE_D);
+ assert(!IS_DWORD(src1));
}
if (src1.type == BRW_REGISTER_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
- assert(src0.type != BRW_REGISTER_TYPE_UD);
- assert(src0.type != BRW_REGISTER_TYPE_D);
+ assert(!IS_DWORD(src0));
}
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
@@ -1222,25 +1217,20 @@ brw_MUL(struct brw_codegen *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
{
/* 6.32.38: mul */
- if (src0.type == BRW_REGISTER_TYPE_D ||
- src0.type == BRW_REGISTER_TYPE_UD ||
- src1.type == BRW_REGISTER_TYPE_D ||
- src1.type == BRW_REGISTER_TYPE_UD) {
+ if (IS_DWORD(src0) || IS_DWORD(src1)) {
assert(dest.type != BRW_REGISTER_TYPE_F);
}
if (src0.type == BRW_REGISTER_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
- assert(src1.type != BRW_REGISTER_TYPE_UD);
- assert(src1.type != BRW_REGISTER_TYPE_D);
+ assert(!IS_DWORD(src1));
}
if (src1.type == BRW_REGISTER_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
- assert(src0.type != BRW_REGISTER_TYPE_UD);
- assert(src0.type != BRW_REGISTER_TYPE_D);
+ assert(!IS_DWORD(src0));
}
assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 329c15b..aad8d8d 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3475,8 +3475,7 @@ fs_visitor::lower_integer_multiplication()
*
* FINISHME: Don't use source modifiers on src1.
*/
- assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
- mul->src[1].type == BRW_REGISTER_TYPE_UD);
+ assert(IS_DWORD(mul->src[1]));
mul->src[1].type = BRW_REGISTER_TYPE_UW;
mul->src[1].stride *= 2;
diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp b/src/intel/compiler/brw_fs_cmod_propagation.cpp
index 2d50c92..cf5baea 100644
--- a/src/intel/compiler/brw_fs_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_fs_cmod_propagation.cpp
@@ -98,8 +98,7 @@ opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
/* CMP's result is the same regardless of dest type. */
if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
scan_inst->opcode == BRW_OPCODE_CMP &&
- (inst->dst.type == BRW_REGISTER_TYPE_D ||
- inst->dst.type == BRW_REGISTER_TYPE_UD)) {
+ IS_DWORD(inst->dst)) {
inst->remove(block);
progress = true;
break;
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
index cb11739..3ae03ab 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -600,8 +600,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
if (((inst->opcode == BRW_OPCODE_MUL &&
inst->dst.is_accumulator()) ||
inst->opcode == BRW_OPCODE_MACH) &&
- (inst->src[1].type == BRW_REGISTER_TYPE_D ||
- inst->src[1].type == BRW_REGISTER_TYPE_UD))
+ IS_DWORD(inst->src[1]))
break;
inst->src[0] = inst->src[1];
inst->src[1] = val;
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 2ade486..2b74f61 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1470,10 +1470,8 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
struct brw_reg src0,
struct brw_reg src1)
{
- assert(dst.type == BRW_REGISTER_TYPE_D ||
- dst.type == BRW_REGISTER_TYPE_UD);
- assert(src0.type == BRW_REGISTER_TYPE_D ||
- src0.type == BRW_REGISTER_TYPE_UD);
+ assert(IS_DWORD(dst));
+ assert(IS_DWORD(src0));
struct brw_reg reg = stride(src1, 1, 4, 0);
if (devinfo->gen >= 8 || inst->exec_size == 8) {
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 876b103..e1e96d7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1579,7 +1579,7 @@ emit_pixel_interpolater_send(const fs_builder &bld,
static fs_reg
intexp2(const fs_builder &bld, const fs_reg &x)
{
- assert(x.type == BRW_REGISTER_TYPE_UD || x.type == BRW_REGISTER_TYPE_D);
+ assert(IS_DWORD(x));
fs_reg result = bld.vgrf(x.type, 1);
fs_reg one = bld.vgrf(x.type, 1);
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index a641ebf..4e95e63 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -970,10 +970,6 @@ vec4_visitor::move_push_constants_to_pull_constants()
bool
vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
{
-#define IS_DWORD(reg) \
- (reg.type == BRW_REGISTER_TYPE_UD || \
- reg.type == BRW_REGISTER_TYPE_D)
-
#define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
/* From the Cherryview and Broadwell PRMs:
@@ -999,7 +995,6 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
}
#undef IS_64BIT
-#undef IS_DWORD
if (devinfo->gen >= 8) {
if (inst->opcode == BRW_OPCODE_F32TO16)
diff --git a/src/intel/compiler/brw_vec4_cmod_propagation.cpp b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
index 4454cdb..9b50c3d 100644
--- a/src/intel/compiler/brw_vec4_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
@@ -85,8 +85,7 @@ opt_cmod_propagation_local(bblock_t *block)
/* CMP's result is the same regardless of dest type. */
if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
scan_inst->opcode == BRW_OPCODE_CMP &&
- (inst->dst.type == BRW_REGISTER_TYPE_D ||
- inst->dst.type == BRW_REGISTER_TYPE_UD)) {
+ IS_DWORD(inst->dst)) {
inst->remove(block);
progress = true;
break;
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 334933d..cf76069 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -807,7 +807,7 @@ generate_tcs_input_urb_offsets(struct brw_codegen *p,
/* If `vertex` is not an immediate, we clobber a0.0 */
assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
- assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
+ assert(IS_DWORD(vertex));
assert(dst.file == BRW_GENERAL_REGISTER_FILE);
--
2.9.3
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