[Mesa-dev] [PATCH 04/16] i965: Add a cache_coherent field to brw_bo

[Chris Wilson]

On Wed, May 24, 2017 at 01:04:46PM -0700, Matt Turner wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_bufmgr.c        | 1 +
>  src/mesa/drivers/dri/i965/brw_bufmgr.h        | 5 +++++
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
>  3 files changed, 9 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> index 9a65d32..2b42182 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -351,6 +351,7 @@ retry:
>     bo->name = name;
>     p_atomic_set(&bo->refcount, 1);
>     bo->reusable = true;
> +   bo->cache_coherent = bufmgr->has_llc;

Another place to consider is on importing or after exporting a bo as it
may have been used for a scanout by the third party, or they may have
given you a snooped bo. I'm not sure how much of that is covered by the
miptree flag.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre