[Mesa-dev] [PATCH 23/30] i965: Move depth to the new resolve functions

Jason Ekstrand jason at jlekstrand.net
Fri May 26 23:30:27 UTC 2017


---
 src/mesa/drivers/dri/i965/brw_clear.c         | 12 ++++++------
 src/mesa/drivers/dri/i965/brw_context.c       |  7 ++++---
 src/mesa/drivers/dri/i965/brw_draw.c          | 17 +++++++++--------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 ++++++++++++++++++++++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  9 +++++++++
 5 files changed, 50 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 9f4a7e6..aa2e994 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -237,13 +237,13 @@ brw_fast_clear_depth(struct gl_context *ctx)
     * buffer.
     */
    if (fb->MaxNumLayers > 0) {
-      for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
-         intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level,
-                                                     depth_irb->mt_layer + layer);
-      }
+      intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
+                                  depth_irb->mt_layer, depth_irb->layer_count,
+                                  ISL_AUX_STATE_CLEAR);
    } else {
-      intel_miptree_slice_set_needs_depth_resolve(mt, depth_irb->mt_level,
-                                                  depth_irb->mt_layer);
+      intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
+                                  depth_irb->mt_layer, 1,
+                                  ISL_AUX_STATE_CLEAR);
    }
 
    return true;
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index ed57012..a61a368 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -204,9 +204,10 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
    /* Resolve the depth buffer's HiZ buffer. */
    depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
    if (depth_irb && depth_irb->mt) {
-      intel_miptree_slice_resolve_hiz(brw, depth_irb->mt,
-                                      depth_irb->mt_level,
-                                      depth_irb->mt_layer);
+      intel_miptree_prepare_depth(brw, depth_irb->mt,
+                                  depth_irb->mt_level,
+                                  depth_irb->mt_layer,
+                                  depth_irb->layer_count);
    }
 
    memset(brw->draw_aux_buffer_disabled, 0,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 07f1d48..a63ae88 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -374,15 +374,16 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
       back_irb->need_downsample = true;
    if (depth_irb && brw_depth_writes_enabled(brw)) {
       if (depth_att->Layered) {
-         for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
-            intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
-                                                        depth_irb->mt_level,
-                                                        depth_irb->mt_layer + layer);
-         }
+         intel_miptree_finish_depth(brw, depth_irb->mt,
+                                    depth_irb->mt_level,
+                                    depth_irb->mt_layer,
+                                    depth_irb->layer_count,
+                                    true);
       } else {
-         intel_miptree_slice_set_needs_depth_resolve(depth_irb->mt,
-                                                     depth_irb->mt_level,
-                                                     depth_irb->mt_layer);
+         intel_miptree_finish_depth(brw, depth_irb->mt,
+                                    depth_irb->mt_level,
+                                    depth_irb->mt_layer, 1,
+                                    true);
       }
       brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
    }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5739508..c17aba9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2501,7 +2501,28 @@ intel_miptree_finish_render(struct brw_context *brw,
 {
    assert(_mesa_is_format_color_format(mt->format));
    intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
-                              mt->mcs_buf);
+                              mt->mcs_buf != NULL);
+}
+
+void
+intel_miptree_prepare_depth(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count)
+{
+   intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+                                mt->hiz_buf != NULL, mt->hiz_buf != NULL);
+}
+
+void
+intel_miptree_finish_depth(struct brw_context *brw,
+                           struct intel_mipmap_tree *mt, uint32_t level,
+                           uint32_t start_layer, uint32_t layer_count,
+                           bool depth_written)
+{
+   if (depth_written) {
+      intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
+                                 mt->hiz_buf != NULL);
+   }
 }
 
 /**
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2136eff..7ddd943 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -1031,6 +1031,15 @@ void
 intel_miptree_finish_render(struct brw_context *brw,
                             struct intel_mipmap_tree *mt, uint32_t level,
                             uint32_t start_layer, uint32_t layer_count);
+void
+intel_miptree_prepare_depth(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt, uint32_t level,
+                            uint32_t start_layer, uint32_t layer_count);
+void
+intel_miptree_finish_depth(struct brw_context *brw,
+                           struct intel_mipmap_tree *mt, uint32_t level,
+                           uint32_t start_layer, uint32_t layer_count,
+                           bool depth_written);
 
 void
 intel_miptree_make_shareable(struct brw_context *brw,
-- 
2.5.0.400.gff86faf



More information about the mesa-dev mailing list