[Mesa-dev] [PATCH 19/30] i965: Move color rendering to the new resolve functions
Jason Ekstrand
jason at jlekstrand.net
Wed May 31 00:59:51 UTC 2017
On Fri, May 26, 2017 at 4:30 PM, Jason Ekstrand <jason at jlekstrand.net>
wrote:
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 35 +++----------------
> src/mesa/drivers/dri/i965/brw_draw.c | 4 +--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 48
> +++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 +++++
> 4 files changed, 63 insertions(+), 33 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 07ddaf0..48e8b6c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -301,38 +301,11 @@ intel_update_state(struct gl_context * ctx, GLuint
> new_state)
> if (irb == NULL || irb->mt == NULL)
> continue;
>
> - struct intel_mipmap_tree *mt = irb->mt;
> + intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
> + irb->mt_layer, irb->layer_count,
> + ctx->Color.sRGBEnabled);
>
> - /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any
> of
> - * the single-sampled color renderbuffers because the CCS buffer
> isn't
> - * supported for SRGB formats. This only matters if
> FRAMEBUFFER_SRGB is
> - * enabled because otherwise the surface state will be programmed
> with
> - * the linear equivalent format anyway.
> - */
> - if (brw->gen >= 9 && ctx->Color.sRGBEnabled && mt->num_samples <= 1
> &&
> - _mesa_get_srgb_format_linear(mt->format) != mt->format) {
> -
> - /* Lossless compression is not supported for SRGB formats, it
> - * should be impossible to get here with such surfaces.
> - */
> - assert(!intel_miptree_is_lossless_compressed(brw, mt));
> - intel_miptree_all_slices_resolve_color(brw, mt, 0);
> - brw_render_cache_set_check_flush(brw, mt->bo);
> - }
> -
> - /* For layered rendering non-compressed fast cleared buffers need
> to be
> - * resolved. Surface state can carry only one fast color clear value
> - * while each layer may have its own fast clear color value. For
> - * compressed buffers color value is available in the color buffer.
> - */
> - if (irb->layer_count > 1 &&
> - !(irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
> - !intel_miptree_is_lossless_compressed(brw, mt)) {
> - assert(brw->gen >= 8);
> -
> - intel_miptree_resolve_color(brw, mt, irb->mt_level, 1,
> - irb->mt_layer, irb->layer_count, 0);
> - }
> + brw_render_cache_set_check_flush(brw, irb->mt->bo);
>
This render_cache_set_check_flush is unneeded and is actually the cause of
most of the performance regressions in this series. Making it
unconditional meant we flushed the render cache on every draw call. It's a
bit surprising that doing so didn't hurt things any worse than it did. It
was originally put in to satisfy the requirements about flushing around
resolves. Now that we do that directly in brw_blorp_resolve_color, we
don't need it at all much less unconditionally. I've removed this line
locally.
> }
>
> _mesa_lock_context_textures(ctx);
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
> b/src/mesa/drivers/dri/i965/brw_draw.c
> index 3a1bb50..07f1d48 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -400,8 +400,8 @@ brw_postdraw_set_buffers_need_resolve(struct
> brw_context *brw)
> continue;
>
> brw_render_cache_set_add_bo(brw, irb->mt->bo);
> - intel_miptree_used_for_rendering(
> - brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count);
> + intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
> + irb->mt_layer, irb->layer_count);
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 8cf2016..1774ed5 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2424,6 +2424,54 @@ intel_miptree_prepare_texture(struct brw_context
> *brw,
> *aux_supported_out = aux_supported;
> }
>
> +void
> +intel_miptree_prepare_render(struct brw_context *brw,
> + struct intel_mipmap_tree *mt, uint32_t level,
> + uint32_t start_layer, uint32_t layer_count,
> + bool srgb_enabled)
> +{
> + /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
> + * the single-sampled color renderbuffers because the CCS buffer isn't
> + * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
> + * enabled because otherwise the surface state will be programmed with
> + * the linear equivalent format anyway.
> + */
> + if (brw->gen >= 9 && srgb_enabled && mt->num_samples <= 1 &&
> + _mesa_get_srgb_format_linear(mt->format) != mt->format) {
> +
> + /* Lossless compression is not supported for SRGB formats, it
> + * should be impossible to get here with such surfaces.
> + */
> + assert(!intel_miptree_is_lossless_compressed(brw, mt));
> + intel_miptree_prepare_access(brw, mt, level, 1, start_layer,
> layer_count,
> + false, false);
> + }
> +
> + /* For layered rendering non-compressed fast cleared buffers need to be
> + * resolved. Surface state can carry only one fast color clear value
> + * while each layer may have its own fast clear color value. For
> + * compressed buffers color value is available in the color buffer.
> + */
> + if (layer_count > 1 &&
> + !(mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
> + !intel_miptree_is_lossless_compressed(brw, mt)) {
> + assert(brw->gen >= 8);
> +
> + intel_miptree_prepare_access(brw, mt, level, 1, start_layer,
> layer_count,
> + false, false);
> + }
> +}
> +
> +void
> +intel_miptree_finish_render(struct brw_context *brw,
> + struct intel_mipmap_tree *mt, uint32_t level,
> + uint32_t start_layer, uint32_t layer_count)
> +{
> + assert(_mesa_is_format_color_format(mt->format));
> + intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
> + mt->mcs_buf);
> +}
> +
> /**
> * Make it possible to share the BO backing the given miptree with another
> * process or another miptree.
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 61ec895..0392935 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -1015,6 +1015,15 @@ intel_miptree_prepare_texture(struct brw_context
> *brw,
> struct intel_mipmap_tree *mt,
> mesa_format view_format,
> bool *aux_supported_out);
> +void
> +intel_miptree_prepare_render(struct brw_context *brw,
> + struct intel_mipmap_tree *mt, uint32_t level,
> + uint32_t start_layer, uint32_t layer_count,
> + bool srgb_enabled);
> +void
> +intel_miptree_finish_render(struct brw_context *brw,
> + struct intel_mipmap_tree *mt, uint32_t level,
> + uint32_t start_layer, uint32_t layer_count);
>
> void
> intel_miptree_make_shareable(struct brw_context *brw,
> --
> 2.5.0.400.gff86faf
>
>
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