[Mesa-dev] [PATCH 2/2] genxml/anv: enable MI_LOAD_REGISTER* to load more than 1 register
Lionel Landwerlin
lionel.g.landwerlin at intel.com
Wed May 31 09:32:53 UTC 2017
The kernel already uses that feature and it would be nice to have
aubinator be able to dump those.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
src/intel/genxml/gen4.xml | 10 ++++++--
src/intel/genxml/gen5.xml | 10 ++++++--
src/intel/genxml/gen6.xml | 10 ++++++--
src/intel/genxml/gen7.xml | 20 ++++++++++++----
src/intel/genxml/gen75.xml | 30 +++++++++++++++++++-----
src/intel/genxml/gen8.xml | 36 +++++++++++++++++++++-------
src/intel/genxml/gen9.xml | 36 +++++++++++++++++++++-------
src/intel/vulkan/gen8_cmd_buffer.c | 21 ++++++++++-------
src/intel/vulkan/genX_cmd_buffer.c | 39 +++++++++++++++++++++----------
src/intel/vulkan/genX_gpu_memcpy.c | 10 ++++----
src/intel/vulkan/genX_query.c | 48 +++++++++++++++++++++++++-------------
11 files changed, 196 insertions(+), 74 deletions(-)
diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index b6721ac9f6c..4d73509d4f6 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -816,6 +816,11 @@
<field name="Global Depth Offset Scale" start="224" end="255" type="float"/>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="6">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -1072,8 +1077,9 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="5" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="63" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="5">
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 729137c666e..8bbf6308c8a 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -934,6 +934,11 @@
<field name="GRF Register Count 3" start="321" end="323" type="uint"/>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="6">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -1186,8 +1191,9 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="5" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="63" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="5">
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 66b45ca7ee2..52c02983279 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -715,6 +715,11 @@
<field name="Non-normalized Coordinate Enable" start="96" end="96" type="bool"/>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="6">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -1750,8 +1755,9 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="54" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 169db321656..95de2421e20 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -789,6 +789,16 @@
<field name="TCZ Address Control Mode" start="96" end="98" type="uint"/>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_MEM_ENTRY" length="2">
+ <field name="Register Address" start="2" end="22" type="offset"/>
+ <field name="Memory Address" start="34" end="63" type="address"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="7">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -2239,8 +2249,9 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="54" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">
@@ -2249,8 +2260,9 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
- <field name="Memory Address" start="66" end="95" type="address"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_MEM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_NOOP" bias="1" length="1">
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index c923189bc62..32c97d556f7 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -873,6 +873,21 @@
</field>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_MEM_ENTRY" length="2">
+ <field name="Register Address" start="2" end="22" type="offset"/>
+ <field name="Memory Address" start="34" end="63" type="address"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_REG_ENTRY" length="2">
+ <field name="Source Register Address" start="2" end="22" type="offset"/>
+ <field name="Destination Register Address" start="34" end="54" type="offset"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="7">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -2597,8 +2612,9 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="54" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">
@@ -2607,16 +2623,18 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
- <field name="Memory Address" start="66" end="95" type="address"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_MEM_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_REGISTER_REG" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86" type="offset"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="64" type="MI_LOAD_REGISTER_REG_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 0b1e81e389d..ddf896e7a88 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -942,6 +942,21 @@
</field>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_MEM_ENTRY" length="3">
+ <field name="Register Address" start="2" end="22" type="offset"/>
+ <field name="Memory Address" start="34" end="95" type="address"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_REG_ENTRY" length="2">
+ <field name="Source Register Address" start="2" end="22" type="offset"/>
+ <field name="Destination Register Address" start="34" end="54" type="offset"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="7">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -2820,31 +2835,34 @@
<field name="Source Memory Address" start="98" end="159" type="address"/>
</instruction>
- <instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">
+ <instruction name="MI_LOAD_REGISTER_IMM" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="54" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
- <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">
+ <instruction name="MI_LOAD_REGISTER_MEM" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="41"/>
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
- <field name="Memory Address" start="66" end="127" type="address"/>
+ <group count="0" start="32" size="96">
+ <field name="Entry" start="0" end="95" type="MI_LOAD_REGISTER_MEM_ENTRY" />
+ </group>
</instruction>
- <instruction name="MI_LOAD_REGISTER_REG" bias="2" length="3">
+ <instruction name="MI_LOAD_REGISTER_REG" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86" type="offset"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_REG_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index d0e85af9c8a..2411a47dbbc 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1000,6 +1000,21 @@
</field>
</struct>
+ <struct name="MI_LOAD_REGISTER_IMM_ENTRY" length="2">
+ <field name="Register Offset" start="2" end="22" type="offset"/>
+ <field name="Data DWord" start="32" end="63" type="uint"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_MEM_ENTRY" length="3">
+ <field name="Register Address" start="2" end="22" type="offset"/>
+ <field name="Memory Address" start="34" end="95" type="address"/>
+ </struct>
+
+ <struct name="MI_LOAD_REGISTER_REG_ENTRY" length="2">
+ <field name="Source Register Address" start="2" end="22" type="offset"/>
+ <field name="Destination Register Address" start="34" end="54" type="offset"/>
+ </struct>
+
<instruction name="3DPRIMITIVE" bias="2" length="7">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
@@ -3105,31 +3120,34 @@
<field name="Force Media Awake" start="32" end="32" type="uint"/>
</instruction>
- <instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">
+ <instruction name="MI_LOAD_REGISTER_IMM" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Offset" start="34" end="54" type="offset"/>
- <field name="Data DWord" start="64" end="95" type="uint"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_IMM_ENTRY" />
+ </group>
</instruction>
- <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">
+ <instruction name="MI_LOAD_REGISTER_MEM" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="41"/>
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
- <field name="Memory Address" start="66" end="127" type="address"/>
+ <group count="0" start="32" size="96">
+ <field name="Entry" start="0" end="95" type="MI_LOAD_REGISTER_MEM_ENTRY" />
+ </group>
</instruction>
- <instruction name="MI_LOAD_REGISTER_REG" bias="2" length="3">
+ <instruction name="MI_LOAD_REGISTER_REG" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86" type="offset"/>
+ <group count="0" start="32" size="64">
+ <field name="Entry" start="0" end="63" type="MI_LOAD_REGISTER_REG_ENTRY" />
+ </group>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index 52412064a95..a9be8cdc26a 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -127,16 +127,20 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
pc.RenderTargetCacheFlushEnable = true;
}
+ uint32_t *p = anv_batch_emitn(&cmd_buffer->batch,
+ 1 + GENX(MI_LOAD_REGISTER_IMM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_IMM));
+ struct GENX(MI_LOAD_REGISTER_IMM_ENTRY) lri;
+
#if GEN_GEN == 9
uint32_t cache_mode;
anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
.STCPMAOptimizationEnable = enable,
.STCPMAOptimizationEnableMask = true);
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(CACHE_MODE_0_num);
- lri.DataDWord = cache_mode;
- }
+
+ lri.RegisterOffset = GENX(CACHE_MODE_0_num);
+ lri.DataDWord = cache_mode;
#elif GEN_GEN == 8
@@ -146,13 +150,14 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
.NPEarlyZFailsDisable = enable,
.NPPMAFixEnableMask = true,
.NPEarlyZFailsDisableMask = true);
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(CACHE_MODE_1_num);
- lri.DataDWord = cache_mode;
- }
+
+ lri.RegisterOffset = GENX(CACHE_MODE_1_num);
+ lri.DataDWord = cache_mode;
#endif /* GEN_GEN == 8 */
+ GENX(MI_LOAD_REGISTER_IMM_ENTRY_pack)(&cmd_buffer->batch, &p[1], &lri);
+
/* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
* Flush bits is often necessary. We do it regardless because it's easier.
* The render cache flush is also necessary if stencil writes are enabled.
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 072d0d50325..48308f4d97e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -36,29 +36,44 @@ static void
emit_lrm(struct anv_batch *batch,
uint32_t reg, struct anv_bo *bo, uint32_t offset)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg;
- lrm.MemoryAddress = (struct anv_address) { bo, offset };
- }
+ uint32_t *p = anv_batch_emitn(batch,
+ 1 + GENX(MI_LOAD_REGISTER_MEM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_MEM));
+
+ GENX(MI_LOAD_REGISTER_MEM_ENTRY_pack)(batch, &p[1],
+ &(struct GENX(MI_LOAD_REGISTER_MEM_ENTRY)) {
+ .RegisterAddress = reg,
+ .MemoryAddress = (struct anv_address) { bo, offset },
+ });
}
static void
emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = reg;
- lri.DataDWord = imm;
- }
+ uint32_t *dw = anv_batch_emitn(batch,
+ 1 + GENX(MI_LOAD_REGISTER_IMM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_IMM));
+
+ GENX(MI_LOAD_REGISTER_IMM_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_IMM_ENTRY)) {
+ .RegisterOffset = reg,
+ .DataDWord = imm,
+ });
}
#if GEN_IS_HASWELL || GEN_GEN >= 8
static void
emit_lrr(struct anv_batch *batch, uint32_t dst, uint32_t src)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
- lrr.SourceRegisterAddress = src;
- lrr.DestinationRegisterAddress = dst;
- }
+ uint32_t *dw = anv_batch_emitn(batch,
+ 1 + GENX(MI_LOAD_REGISTER_REG_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_REG));
+
+ GENX(MI_LOAD_REGISTER_REG_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_REG_ENTRY)) {
+ .SourceRegisterAddress = src,
+ .DestinationRegisterAddress = dst,
+ });
}
#endif
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c
index 3cbc7235cfc..74e02bd15d8 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -182,10 +182,12 @@ genX(cmd_buffer_gpu_memcpy)(struct anv_cmd_buffer *cmd_buffer,
#if GEN_GEN <= 7
/* The hardware can do this for us on BDW+ (see above) */
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
- load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);
- load.DataDWord = 0;
- }
+ dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(MI_LOAD_REGISTER_IMM));
+ GENX(MI_LOAD_REGISTER_IMM_ENTRY_pack)(&cmd_buffer->batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_IMM_ENTRY)) {
+ .RegisterOffset = GENX(SO_WRITE_OFFSET0_num),
+ .DataDWord = 0,
+ });
#endif
dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 5102412e8f9..86ab1890a92 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -528,23 +528,35 @@ static void
emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
struct anv_bo *bo, uint32_t offset)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg,
- lrm.MemoryAddress = (struct anv_address) { bo, offset };
- }
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg + 4;
- lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
- }
+ uint32_t *dw;
+
+ dw = anv_batch_emitn(batch, 1 + GENX(MI_LOAD_REGISTER_MEM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_MEM));
+ GENX(MI_LOAD_REGISTER_MEM_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_MEM_ENTRY)) {
+ .RegisterAddress = reg,
+ .MemoryAddress = (struct anv_address) { bo, offset },
+ });
+ dw = anv_batch_emitn(batch, 1 + GENX(MI_LOAD_REGISTER_MEM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_MEM));
+ GENX(MI_LOAD_REGISTER_MEM_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_MEM_ENTRY)) {
+ .RegisterAddress = reg + 4,
+ .MemoryAddress = (struct anv_address) { bo, offset + 4 },
+ });
}
static void
emit_load_alu_reg_imm32(struct anv_batch *batch, uint32_t reg, uint32_t imm)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = reg;
- lri.DataDWord = imm;
- }
+ uint32_t *dw = anv_batch_emitn(batch,
+ 1 + GENX(MI_LOAD_REGISTER_IMM_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_IMM));
+ GENX(MI_LOAD_REGISTER_IMM_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_IMM_ENTRY)) {
+ .RegisterOffset = reg,
+ .DataDWord = imm,
+ });
}
static void
@@ -557,10 +569,14 @@ emit_load_alu_reg_imm64(struct anv_batch *batch, uint32_t reg, uint64_t imm)
static void
emit_load_alu_reg_reg32(struct anv_batch *batch, uint32_t src, uint32_t dst)
{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
- lrr.SourceRegisterAddress = src;
- lrr.DestinationRegisterAddress = dst;
- }
+ uint32_t *dw = anv_batch_emitn(batch,
+ 1 + GENX(MI_LOAD_REGISTER_REG_ENTRY_length),
+ GENX(MI_LOAD_REGISTER_REG));
+ GENX(MI_LOAD_REGISTER_REG_ENTRY_pack)(batch, &dw[1],
+ &(struct GENX(MI_LOAD_REGISTER_REG_ENTRY)) {
+ .SourceRegisterAddress = src,
+ .DestinationRegisterAddress = dst,
+ });
}
/*
--
2.11.0
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