[Mesa-dev] [PATCH v3 29/43] i965/fs: Unpack 16-bit from 32-bit components in VS load_input

[Jason Ekstrand]

On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasanova at igalia.com> wrote:

> The VS load input for 16-bit values receives pairs of 16-bit values
> packed in 32-bit values. Because of the adjusted format used at:
>
>  anv/pipeline: Use 32-bit surface formats for 16-bit formats
>
> v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index d2f2e17b70..83ff0607a7 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -2322,8 +2322,25 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder
> &bld,
>        assert(const_offset && "Indirect input loads not allowed");
>        src = offset(src, bld, const_offset->u32[0]);
>
> -      for (unsigned j = 0; j < num_components; j++) {
> -         bld.MOV(offset(dest, bld, j), offset(src, bld, j +
> first_component));
> +      /* The VS load input for 16-bit values receives pairs of 16-bit
> values
> +       * packed in 32-bit values. This is an example on SIMD8:
> +       *
> +       * xy xy xy xy xy xy xy xy
> +       * zw zw zw zw yw zw zw xw
> +       *
> +       * We need to format it to something like:
> +       *
> +       * xx xx xx xx yy yy yy yy
> +       * zz zz zz zz ww ww ww ww
> +       */
>

Please pull this comment inside the if.


> +      if (type_sz(type) == 2) {
> +         for (unsigned j = 0; j < num_components; j++)
> +            bld.MOV(offset(dest, bld, j),
> +                    subscript(retype(offset(src,bld, (j / 2) * 2 +
> first_component),
>
+                                     BRW_REGISTER_TYPE_F), type, j % 2));


Ugh... This is rather hard to parse.  All of the retyping and subscripting
is making my head spin.  How about:

src.type = BRW_REGISTER_TYPE_F;
for (unsigned j = 0; j < num_components; j++) {
   unsigned src_comp = j / 2 + first_component;
   bld.MOV(offset(dest, bld, j),
             subscript(offset(src, bld, src_comp), dst.type, j % 2));
}


> +      } else {
> +         for (unsigned j = 0; j < num_components; j++)
> +            bld.MOV(offset(dest, bld, j), offset(src, bld, j +
> first_component));
>        }
>
>        if (type == BRW_REGISTER_TYPE_DF) {
> --
> 2.13.6
>
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