[Mesa-dev] [PATCH 4/4] intel/fs/nir: Return Q types from brw_reg_type_for_bit_size

[Jason Ekstrand]

Now that we're returning a sane type, we can drop the retyping to Q in
nir_emit_load_const.

Cc: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
---
 src/intel/compiler/brw_fs_nir.cpp | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index cbd51a9..0b17e4f 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -264,7 +264,7 @@ brw_reg_type_from_bit_size(const unsigned bit_size,
       case 32:
          return BRW_REGISTER_TYPE_D;
       case 64:
-         return BRW_REGISTER_TYPE_DF;
+         return BRW_REGISTER_TYPE_Q;
       default:
          unreachable("Invalid bit size");
       }
@@ -277,7 +277,7 @@ brw_reg_type_from_bit_size(const unsigned bit_size,
       case 32:
          return BRW_REGISTER_TYPE_UD;
       case 64:
-         return BRW_REGISTER_TYPE_DF;
+         return BRW_REGISTER_TYPE_UQ;
       default:
          unreachable("Invalid bit size");
       }
@@ -1420,8 +1420,7 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld,
          }
       } else {
          for (unsigned i = 0; i < instr->def.num_components; i++)
-            bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_Q),
-                    brw_imm_q(instr->value.i64[i]));
+            bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value.i64[i]));
       }
       break;
 
-- 
2.5.0.400.gff86faf