[Mesa-dev] [PATCH v2 3/4] i965/gen10: Enable float blend optimization

[Nanley Chery]

On Fri, Nov 03, 2017 at 11:39:34AM -0700, Anuj Phogat wrote:
> On Fri, Nov 3, 2017 at 9:46 AM, Nanley Chery <nanleychery at gmail.com> wrote:
> > On Wed, Nov 01, 2017 at 03:50:54PM -0700, Anuj Phogat wrote:
> >> This optimization is enabled for previous generations too.
> >> See Mesa commit c17e214a6b
> >> On CNL this bit has been moved to CACHE_MODE_SS register.
> >>
> >> Cc: Nanley Chery <nanley.g.chery at intel.com>
> >> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> >> ---
> >>  src/mesa/drivers/dri/i965/brw_defines.h      | 3 +++
> >>  src/mesa/drivers/dri/i965/brw_state_upload.c | 6 ++++++
> >>  2 files changed, 9 insertions(+)
> >>
> >> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> >> index 270cdf29db..3008a1b8a7 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> >> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> >> @@ -1688,6 +1688,9 @@ enum brw_pixel_shader_coverage_mask_mode {
> >>  # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
> >>  # define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
> >>
> >> +#define GEN10_CACHE_MODE_SS            0x0e420
> >> +# define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> >     ^
> >     extra space
> Fixed.
> >> +
> >
> > GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE has the same value as
> > GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE. This seems like something we'd
> > normally reeuse.
> >
> This header has a format of defining the register followed by defining
> the bits in it. I think defining a new macro for gen 10 makes it more
> clear that this bit is now the part of CACHE_MODE_SS register.
> 

Sounds good to me.

> 
> >>  #define INSTPM                             0x20c0
> >>  # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
> >>
> >> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> >> index 23e4ebda25..7df06a6e4d 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> >> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> >> @@ -85,6 +85,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> >>        }
> >>     }
> >>
> >> +   if (devinfo->gen == 10) {
> >> +      brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
> >> +                              REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
> >> +                              GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
> >> +   }
> >> +
> >>     if (devinfo->gen >= 8) {
> >>        gen8_emit_3dstate_sample_pattern(brw);
> >>
> >> --
> >> 2.13.5
> >>
> >> _______________________________________________
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