[Mesa-dev] Mesa 17.2.5 release candidate

Wed Nov 8 23:37:43 UTC 2017

Hello list,

The candidate for the Mesa 17.2.5 is now available. Currently we have:
 - 30 queued
 - 16 nominated (outstanding)
 - and 3 rejected patches

In the current queue we have:

In Mesa Core a GL error related to the ARB_ES3_1_compatibility spec
noticed with the GFXBench 5 Aztec Ruins has been corrected. 

The GLSL compiler is not giving a linker error for mismatching uniform
precision with GLSL ES 1.00 any more. This enables, specially, several
Android applications which violate this rule, like Forge of Empires,
for example.

The SPIR-V compiler has corrected an assert triggered when support for
the simple memory model was claimed.

NIR has also received a correction related with
gl_SubGroupG{e,t}MaskARB.

The Intel drivers, specially i965, have received several fixes,
including a plug for a memory leak and another one in the compiler to
avoid GPU hangs on Broxton.

The gallium i915g driver for Intel has also seen an important
correction.

AMD drivers, mostly radv, have also received several fixes, including a
correction for a DCC corruption that was visible with Rust, breaking an
endless loop in r600, avoiding a GPU hang with vulkan dota2 in VR mode
and a plug for a memory leak.

Broadcom's vc4 has gotten a fix to compile out some non-debug code that
shouldn't be there for the release build.

Take a look at section "Mesa stable queue" for more information.

Testing reports/general approval
--------------------------------

Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.

The plan is to have 17.2.5 next Friday (10th of November), around or
shortly after 23:00 GMT.

If you have any questions or suggestions - be that about the current
patch queue or otherwise, please go ahead.

Trivial merge conflicts
-----------------------

commit e7ddddc9892810b65bda232a00f798aa4a258fc8
Author: Jason Ekstrand <jason.ekstrand at intel.com>

    i965/miptree: Take an isl_format in render_aux_usage

    (cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39)

commit bd2037da82ec8abc1db8834f67496b4b3cd74504
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

    radv: Don't expose heaps with 0 memory.

    (cherry picked from commit 806721429afa090380bf39a4958fe4e21c63816c)

commit 23eaeeb88ad787b0e3253807fb6f7180a0cb0711
Author: Dave Airlie <airlied at redhat.com>

    radv: free attachments on end command buffer.

    (cherry picked from commit f0ae06a13c1a60f58de77401f705eaf620b5b822)

commit 9ba45e7d33bb91d7b0fc65ecae9cbc8a2ba68593
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

    radv: Don't use vgpr indexing for outputs on GFX9.

    (cherry picked from commit 6ce550453f1df64caeb956f215d32da96b89f2b1)

commit 6a73458510c124856ade7e5a7e805fb08ae13671
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

    radv: Disallow indirect outputs for GS on GFX9 as well.

    (cherry picked from commit c07d719e8b683e1bf78f187dd17fe4716f4e5e9c)

Cheers,
Andres

Mesa stable queue
-----------------

Nominated (16)
=============

Emil Velikov (1):
      targets/opencl: don't hardcode the icd file install to /etc/...

Jason Ekstrand (15):
      intel/fs: Use a pure vertical stride for large register strides
      intel/fs: Pass builders instead of blocks into emit_[un]zip
      intel/fs: Be more explicit about our placement of [un]zip
      intel/fs: Use ANY/ALL32 predicates in SIMD32
      intel/fs: Don't stomp f0.1 in SIMD16 ballot
      intel/fs: Use an explicit D type for vote any/all/eq intrinsics
      intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
      intel/eu/reg: Add a subscript() helper
      intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
      intel/fs: Fix integer multiplication lowering for src/dst hazards
      intel/fs: Use the original destination region for int MUL lowering
      intel/fs: Mark 64-bit values as being contiguous
      intel/fs: Rework zero-length URB write handling
      intel/nir: Add a helper for getting the NoIndirect mask
      inte
l/nir: Break the linking code into a helper in brw_nir.c

Queued (30)
===========

Andres Gomez (7):
      docs: add sha256 checksums for 17.2.4
      cherr
y-ignore: radv: copy indirect lowering settings from radeonsi
      cher
ry-ignore: i965: fix blorp stage_prog_data->param leak
      cherry-
ignore: etnaviv: don't do resolve-in-place without valid TS
      cherry
-ignore: intel/fs: Alloc pull constants off mem_ctx
      cherry-ignore: 
added 17.3 nominations.
      cherry-ignore: automake: include
git_sha1.h.in in release tarball

Bas Nieuwenhuizen (3):
      radv: Don't expose heaps with 0 memory.
      radv: Don't use vgpr indexing for outputs on GFX9.
      radv: Disallow indirect outputs for GS on GFX9 as well.

Dave Airlie (3):
      i915g: make gears run again.
      radv: free attachments on end command buffer.
      radv: add initial copy descriptor support. (v2)

Eric Engestrom (1):
      vc4: fix release build

Gert Wollny (1):
      r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling

Jason Ekstrand (4):
      spirv: Claim support for the simple memory model
      i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees
      i965/blorp: Use more temporary isl_format variables
      i965/mip
tree: Take an isl_format in render_aux_usage

Kenneth Graunke (1):
      mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.

Leo Liu (1):
      radeon/video: add gfx9 offsets when rejoin the video surface

Marek Olšák (2):
      st/dri: don't expose modifiers in EGL if the driver doesn't implement them
      ac/surface/gfx9: don't allow DCC for the smallest mipmap levels

Nanley Chery (1):
      i965: Check CCS_E compatibility for texture view rendering

Neil Roberts (1):
      nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB

Nicolai Hähnle (1):
      amd/common/gfx9: workaround DCC corruption more conservatively

Tapani Pälli (1):
      i965: unref push_const_bo in intelDestroyContext

Timothy Arceri (1):
      radv: copy indirect lowering settings from radeonsi

Tomasz Figa (1):
      glsl: Allow precision mismatch on dead data with GLSL ES 1.00

Topi Pohjolainen (1):
      intel/compiler/gen9: Pixel shader header only workaround

Rejected (3)
============

Jason Ekstrand (1):
      intel/fs: Alloc pull constants off mem_ctx

Reason: Commit addressed earlier commit 8d90e28839 which did not land
in branch.

Tapani Pälli (1):
      i965: fix blorp stage_prog_data->param leak

Reason: Commit addressed earlier commit 8d90e28839 which did not land
in branch.

Wladimir J. van der Laan (1):
      etnaviv: don't do resolve-in-place without valid TS

Reason: Commit addressed earlier commit 78ade659569 which did not land
in branch.