[Mesa-dev] [PATCH 2/6] radeonsi: remove r600_texture::non_disp_tiling

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
 src/gallium/drivers/radeon/r600_texture.c     | 7 -------
 2 files changed, 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 47306c6..48501a1 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -256,22 +256,20 @@ struct r600_texture {
 
 	/* Depth buffer compression and fast clear. */
 	uint64_t			htile_offset;
 	bool				tc_compatible_htile;
 	bool				depth_cleared; /* if it was cleared at least once */
 	float				depth_clear_value;
 	bool				stencil_cleared; /* if it was cleared at least once */
 	uint8_t				stencil_clear_value;
 	bool				upgraded_depth; /* upgraded from unorm to Z32_FLOAT */
 
-	bool				non_disp_tiling; /* R600-Cayman only */
-
 	/* Whether the texture is a displayable back buffer and needs DCC
 	 * decompression, which is expensive. Therefore, it's enabled only
 	 * if statistics suggest that it will pay off and it's allocated
 	 * separately. It can't be bound as a sampler by apps. Limited to
 	 * target == 2D and last_level == 0. If enabled, dcc_offset contains
 	 * the absolute GPUVM address, not the relative one.
 	 */
 	struct r600_resource		*dcc_separate_buffer;
 	/* When DCC is temporarily disabled, the separate buffer is here. */
 	struct r600_resource		*last_dcc_separate_buffer;
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 0800c0f..a1b6ed4 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -546,21 +546,20 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
 	rtex->can_sample_s = new_tex->can_sample_s;
 	rtex->surface = new_tex->surface;
 	rtex->fmask = new_tex->fmask;
 	rtex->cmask = new_tex->cmask;
 	rtex->cb_color_info = new_tex->cb_color_info;
 	rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
 	rtex->htile_offset = new_tex->htile_offset;
 	rtex->tc_compatible_htile = new_tex->tc_compatible_htile;
 	rtex->depth_cleared = new_tex->depth_cleared;
 	rtex->stencil_cleared = new_tex->stencil_cleared;
-	rtex->non_disp_tiling = new_tex->non_disp_tiling;
 	rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
 	rtex->framebuffers_bound = new_tex->framebuffers_bound;
 
 	if (new_bind_flag == PIPE_BIND_LINEAR) {
 		assert(!rtex->htile_offset);
 		assert(!rtex->cmask.size);
 		assert(!rtex->fmask.size);
 		assert(!rtex->dcc_offset);
 		assert(!rtex->is_depth);
 	}
@@ -1148,24 +1147,20 @@ r600_texture_create_object(struct pipe_screen *screen,
 			rtex->db_render_format = base->format;
 		else {
 			rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
 			rtex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT &&
 					       base->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT;
 		}
 	} else {
 		rtex->db_render_format = base->format;
 	}
 
-	/* Tiled depth textures utilize the non-displayable tile order.
-	 * This must be done after r600_setup_surface.
-	 * Applies to R600-Cayman. */
-	rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
 	/* Applies to GCN. */
 	rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
 
 	/* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
 	 * between frames, so the only thing that can enable separate DCC
 	 * with DRI2 is multiple slow clears within a frame.
 	 */
 	rtex->ps_draw_ratio = 0;
 
 	if (rtex->is_depth) {
@@ -1484,22 +1479,20 @@ bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 	resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
 
 	if (staging)
 		resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
 
 	*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 	if (*flushed_depth_texture == NULL) {
 		R600_ERR("failed to create temporary texture to hold flushed depth\n");
 		return false;
 	}
-
-	(*flushed_depth_texture)->non_disp_tiling = false;
 	return true;
 }
 
 /**
  * Initialize the pipe_resource descriptor to be of the same size as the box,
  * which is supposed to hold a subregion of the texture "orig" at the given
  * mipmap level.
  */
 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
 					     struct pipe_resource *orig,
-- 
2.7.4