[Mesa-dev] [PATCH 2/2] anv/gen10: Enable float blend optimization

[Anuj Phogat]

On Fri, Nov 10, 2017 at 8:42 AM, Rafael Antognolli
<rafael.antognolli at intel.com> wrote:
> On Thu, Nov 09, 2017 at 11:14:43AM -0800, Anuj Phogat wrote:
>> On CNL this bit has been moved to CACHE_MODE_SS register.
>> We already have this enabled in OpenGL driver.
>> See Mesa commit 6c681b4cc1
>>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> Cc: Nanley Chery <nanley.g.chery at intel.com>
>> Cc: Rafael Antognolli <rafael.antognolli at intel.com>
>> ---
>>  src/intel/genxml/gen10.xml    | 12 ++++++++++++
>>  src/intel/vulkan/genX_state.c | 12 ++++++++++++
>>  2 files changed, 24 insertions(+)
>>
>> diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
>> index a7ae49ae65..a6b8f48fda 100644
>> --- a/src/intel/genxml/gen10.xml
>> +++ b/src/intel/genxml/gen10.xml
>> @@ -3752,4 +3752,16 @@
>>      <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
>>    </register>
>>
>> +  <register name="CACHE_MODE_SS" length="1" num="0x0e420">
>> +    <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/>
>> +    <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/>
>> +    <field name="Float Blend Optimization Enable" start="4" end="4" type="bool"/>
>> +    <field name="Per Sample Blend Opt Disable"  start="11" end="11" type="bool"/>
>> +
>> +    <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool"/>
>> +    <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool"/>
>> +    <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool"/>
>> +    <field name="Per Sample Blend Opt Disable Mask"  start="27" end="27" type="bool"/>
>> +  </register>
>> +
>>  </genxml>
>
> I think we have been adding the genxml changes into their own commits, so it
> may be good to split this part into a separate one. Other than that, looks good
> to me (again waiting on Jason or Nanley).
>
> With the above change,
>
Splitted this patch in to two:
[PATCH 1.5/2] intel/genxml: Add Cache Mode SubSlice Register to gen10.xml
[PATCH 2/2] anv/gen10: Enable float blend optimization

> Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
>
>> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
>> index f56c686ed3..54fb8634fd 100644
>> --- a/src/intel/vulkan/genX_state.c
>> +++ b/src/intel/vulkan/genX_state.c
>> @@ -121,6 +121,18 @@ genX(init_device_state)(struct anv_device *device)
>>     }
>>  #endif
>>
>> +#if GEN_GEN == 10
>> +   uint32_t cache_mode_ss;
>> +   anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS),
>> +                   .FloatBlendOptimizationEnable = true,
>> +                   .FloatBlendOptimizationEnableMask = true);
>> +
>> +   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
>> +      lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
>> +      lri.DataDWord      = cache_mode_ss;
>> +   }
>> +#endif
>> +
>>     anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
>>
>>     anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
>> --
>> 2.13.5
>>